Produzione del chip standard cell AMchip03Per SVT a CDF

• Breve descrizione dei tests del prototipo e risultati

1. il chip funziona (up to now) 2. ma yield e’ basso 3. 37% perfetti, ~55-60% perfetti+ “quasi” perfetti

• Descrizione dell’ upgrade AM++ e sua flessibilita’

• Descrizione diverse possibilita’ di produzione e loro costi Servono almeno 70 kE aggiuntivi

AMchip03 status .• 126 dies produced by IMEC, 116 of which

came packaged. Arrived on September 30th• Simulation test vectors translated for the Test stand.• Test of all the chips in the Test stand

Inputs from Pattern

Generator

Output toLogic

Analyzer

AMChipsocket

The SCAM chip

Test VectorsThree types of tests:• Random Tests: 1) Generate Random Patterns

2) Generate Random Configurations

3) Send random Hits + good hits

• Memory Tests

• Feature Tests1) FSM

2) Jtag

3) Extest I/O

4) Opcode

SCAMChip internal Structure

Pattern Bank

Pattern Flux

Jtag

RoadsFrom AM

Roads to next AMchip

AMchip03 Test: Results

Yield (flawless) ≈ 37%

Yield (flawless + defective Patterns < 2) ≈ 53.5%

Yield (flawless + defective Patterns < 5) ≈ 59.5%

• We passed all the 116 chips through an intensive test at 100 nS.

• 8 AM chips tested @30nS to be mounted on a first LAMB++

Yield Expected 68%, based on IMEC’s predictions.

Yield puo’ fluttuare moltoproduzione calcolata su 35%

1 solo pattern wrong (preliminary tests) = 19/11616.4 %1 < Pattern wrong < 5 = 7/116 6.0%Pattern wrong>4 o other errors = 46/11639.7%

Good = 43/116 37.1%

BLOCCO 0 BLOCCO 1 BLOCCO 2 BLOCCO 3Pattern Layer Chip Pattern Layer Chip Pattern Layer Chip Pattern Layer Chip

0x0 0x800 819 1 34 0x1000 106B 4 8 0x18001000 0 76

0x100 1A3 2 23 0x900 0x1100 1190 2 2 0x1900 19C6 5 1031924 2 6

196C 5-4-1-0 62

0x200 240 1 78 0xA00 AFC ? 18 0x1200 122A 3 25 0x1A0012E0 2 98

0x300 378 4 109 0xB00 B0C 0 1 0x1300 133A 0 9 0x1B001367 2 33

0x400 4CA 1 17 0xC00 C39 ? 87 0x1400 1421 ? 111 0x1C00

0x4FF 0xCFF 0x14FF 0x1CFF

4 4 8 3

Test Stand – Vme CrateA complete system with an AMS/Pulsar, a merger and an AM++ with FPGAs has been tested with success @33MHz.

At the moment we can load 5000 patterns in AMchips and send Random Test Hits + good Hits.

Currently Testing with a Lamb++ equipped with 8 AMchips

Next step: adding a Lamb++ with 16 “defective”AMchips.

# Lambs (16 Amchips)/ SVTupg/ tot keurowedge SVTnow chips

2 Lamb: 160 kpatt/wedge 5 384 53 2003

+ spare ~500

8 Lamb: 640 kpatt/wedge 20 1536 93 2004

+ spare ~2000

Maximum L1 rate for 5% L2 dead time @3x1032

Current SVT Upgraded SVT

13 KHz 23 KHzGain of the 2004SVT upgrade

SVT Phyiscs Triggerrates: examples@3x1032

Trigger L1 Trigger rate

Z b-b 26 KHz

Hadronic B decay 177 KHz

Installazione2005

Eventuale completamento

AM

LAMB GLUE

Input Control

RECEIVERs & DRIVERs

LAMB CONNECTORs

VME INTERFACE

HIT

/RO

AD

CO

NN

EC

TO

R

TOP GLUE

PIPELINEREGISTERs

INDI

ToAMS

ClockDistrib.

AM++ (9U VME)MAX 2005: 640 Kpatt/wedge

Year chip boards devel. Total

2003? 120 kE10 kE (test b.) 5 kE 135 kE

2004 - 10 kE (protot.) 30 kE 40 kE

2005 53 kE 100 kE (produc.) 153 k

+40 kE +40 kE

+70 kE (produzione)

+40 kE tests di qualifica +25 kE package sottile

Upgrade 2004: 600 chipsUpgrade 2005: 2000 chips buoni Ipotesi 35/50% yield – fondi 95 + 60 keuros = 155 ke

Pilot Run: nuove maschere 210 k$ 1 wf 250 chips contro i 38 MPW

PILOT #good costo Mancanti costoRUN chips keuro keuro altrettanti#wafers chip12 1050/1500 215 60 26.4 k$25 2188/3125225 70 55 k$

MPW: buono per piccole produzioni usando mascheredel prototipo

Si paga solo il silicio ed i 5/6 del wafer si buttano!Con 128 wafers 1700/2430 chips - costo=240 keuro

Due strategie di produzione: MPW e Pilot Run

Conclusioni

•Il chip funziona (up to now)

•Yield ~ 37%•Forse si possono usare anche i quasi perfetti: 55-59%

•Yield puo’ fluttuare moltoproduzione calcolata su 35%•Pilot run: migliore garanzia per avere 2000 chips

•Si richiedono 70 keuro aggiuntivi per il pilot run

SVTBackup slides

backup

slides

Upgrade 2004: 600 chipsUpgrade 2005: 2000 chips buoni Ipotesi 35/50% yield – fondi 95 + 60 keuros = 155 ke

MPW #good costo Mancanti costoWafers chips keuro keuro /chip

50 665/950 130 0 184/128.5 E75 998/1425 185 30 177/124 E100 1330/1900190 35 138/96 E128 1700 240 85 138 E

PILOT #good costo Mancanti costoRUN chips keuro keuro /chip

12 1050/1500 215 60 198/139–32/22 E25 2188/3125225 70 101/71 –21/15 E

TsukubaChicago

Tempi di processamento: come agisce l’upgrade ?

Ricetta per velocizzare il tempo di esecuzione di SVT:

1. pattern piu’ sottili (AM grande) meno fits.

2. Road Warrior per rimuovere i ghosts

Hit Finders

Merger

Associative Memory

Hit Buffer

Track Fitter

to Level 2

COT tracks

fromXTRP

12 fibers

hits

roads

hits

x 12 phi sectors

Sequencerraw data fromSVX front end

NUOVA AM piu’ grande

Road Warrior

SVT exec time ~ proporzionale # candidati da fittare

TEMPI DI REALIZZAZIONE• Nuova AM-board: inizio estate 2004 (Pisa) durante estate 2004: test con FPGA (Pisa)

• Progetto prototipo AM-chip: luglio 2004 (Ferrara-Pisa)consegna chip ~2 mesi – disponibile ad ottobre.

• Nuova LAMB: montare nuovo AM-chip a ottobre 2004 (Pisa)

• test del chip + scheda: ottobre – dicembre 2004 (Pisa-Ferrara)

• produzione: inizio 2005 (Pisa-Ferrara)• installazione: estate 2005 (Pisa-Ferrara)• Altri DAQ/Trigger upgrade: previsti nel 2006

Road Warrior: . . . (~60 k$ Fermilab)

messa in opera entro fine 2003 F. Spinella (in funzione)

RW+TF: F>50s = 21%

Mezzanine slotsAUX card

Pulsar

CustomMezzanine

Bottom view

Worksup to

100MHz

Top view

Pulsar (Pulser And Recorder) Design

Three ALTERA APEX 20K400 FPGAs

I/O Mezzanine cards for: S-LINK (CERN/LHC) Hotlink TAXI to be specified

Self-testableModular, lego-style open design Replacing > 10 CDF board types all CDF, many ATLAS connectors/standards

AMchip

L. Zanello

Trigger/DAQ Upgrades for Run IIb• Need to Maintain or increase bandwidth

Luminosity Rate (=L) Luminosity inter/x-ing

Complexity (and fakes) Event Size, Exec. time

– All physics to tape

• L1 Bandwidth (output to L2)– XFT Purity trigger(L1, L2)– SVT, L2 L2 Exec. t L1 Bandwidth

• L2 Bandwidth (output to L3)– COT TDC Readout rate – Level 3 Processing L3 Exec. t– Event Builder Readout rate

• L3 Bandwidth (output to tape)– CSL Tape rate (not under IIb project)