M.Caselle

KIT – Universität des Landes Baden-Württemberg undnationales Forschungszentrum in der Helmholtz-Gemeinschaft

KIT, Institut für Prozessdatenverarbeitung und ElektronikM. Caselle

www.kit.edu

M.Caselle

MOS transistor & introduction to analog layoutKSETA – KIT-Center Elementary Particle and Astroparticle Physics. 06 February 2014

KIT, Institut für Prozessdatenverarbeitung und Elektronik3

n-MOS Field Effect Transistor

Leff

LDrawn

MOS transistor (3D view)

MOS transistor (n-type) – front section

Source DrainGate

P-substrate

n+ n+

P-substrate

SG

D

n+ n+

n+ regions

Metal Oxide (dielectric)Semiconductor (substrate)

MOS transistor (p-type) – front section

N-substrate

SG

D

p+ p+

MOS

Complementary MOS (CMOS) technologies, both n-MOS and p-MOS transistors are available

Weff

KSETA , Karlsruhe 26 February 2013 – M. Caselle

Three terminals device (Source, Drain and Gate)


MOS transistor (n-type) MOS interface capacitance vs. substrate

Drain and source n+ regions diode vs. substrate

G

S

D

NMOS electrical symbol

Electrical considerations:Drain and Source will work as two independent diodes with anode connected to bulkIf VS < 0V and/or VD <0

this suggest that VS and VD must be ≥ 0V

no current flow between Source and DrainIf VG = 0V

What about the MOS interface behaviour …. ?

n-MOS Field Effect Transistor (II)


Substrate at 0V


MOS interface – (IDS vs. Vgs) Characteristics

Drain and Source are connected through with a conductive channel

VTH VGS

IDS+ +

+

+

+

+

+

+++

++

+ + +++ +P-substrate

SG

D

n+ n+

-+

VG < 0Hole accumulation

S D

P-substrate

S GD

n+ n+

Depletion region--+VG > 0

+ ++ ++ + +++

+- - - - -

Negative ions

S D

+-

P-substrate

S G D

n+ n+

++ ++ + ++

++

Inversion layer

- - - - -- - - - -- - - - -

Free electrons

VG > VTH > 0 (threshold voltage)

S D

e- e-e-

OFF

ON


--- ------ ---

++++++++

++++++++


MOS interface – summarize

Drain and Source are connected through with a conductive channel

+ ++

+

+

+

+

+++

++

+ + +++ +P-substrate

S G D

n+ n+

-+

VG < 0

Accumulation region

P-substrate

S GD

n+ n+

Depletion region--+VG > 0

+ ++ ++ + +++

+- - - - -

+-

P-substrate

S G D

n+ n+

+ ++ + + +

Inversion layer

- - - - -- - - - -- - - - -VG > VTH > 0 (threshold voltage)



n-MOS interface – (IDS vs. VDS) Characteristic

Linear or trioderegion

VDS

IDS VGS3

VGS2

VGS1

VDS close to zero

VGS3 > VGS2 > VGS1 > VTH

-+S

VD > 0

P-substrate

n+ n+------

VG > VTH

S D

VG > VTH S D

MOSFET as a controlled linear resistorRon

GChannel modulation

Typical value few hundred Ohms

------

Thickness of the free electrons region depends on VGS

S D

VG > VTH

P-substrate

n+ n+------------

Inversion layer

Free electrons



VDSLarge VDS VDS1 = VGS1 - VTH

Ids1

High resistance

Saturation region

VGS2

VGS1

Ids2

Ids3

VGS3

n-MOS interface – (IDS vs. VDS) Characteristic

-+S

VD > 0

P-substrate

n+ n+------------

VG > VTH

Linear or trioderegion

Channel modulation

VD > 0

IDS

-------

S DG

P-substrate

n+ n+

Saturation region-+

VG > VTH

Channel pinch-off(point with no free charges inside)


S

DVG > VTH

IDS

Drain

Source

IDSRout

Ids = gm * VGS

VDS > VGS - VTH


IDS vs. VDS working regions

High resistance

Saturation region

VDS

IDS

VGS3

VGS2

VGS1Lin

ear r

egio

n VGS ~ 0VVDS any values

S

D IDSG

VGS

VDS

MOS works as a switch (ON)(low serial resistance)

D

S

VGS > VTHVDS > VGS - VTH

D S

MOS works as a switch (OFF)(high resistance of ten/hundred megaohms)Digital Circuit

Analog CircuitVGS > VTHand VDS ~ 0V



P-device is implemented in a N-type well (n-well)

n-well

The CMOS technology

MOS transistor (n-type)

Require P-substrate SG

D

n+ n+

MOS transistor (p-type)

Require a N-substrateSG

D

p+ p+

CMOS technology is used in microprocessors, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, etc..

Complementary MOS (CMOS) is a technology for constructing integrated circuits

In which way it is possible to merge two different transistor typologies on common substrate ?

CMOS inverter (NOT logic gate)p-mos

n-mos

A input signal

Q output signal

Vss could be = 0V

Few µm


0 1 0 1 0 1 0 1 0 1

P- substrate


n-MOS technology layout and physical implementation (I)Step 1 – n+ drain/source region

n+ region (RX)

Transistor channel Width

3D viewLayout view

n+

P- substrate

Step 2 – drain/source metal contact

Drain and Source metal contact (CA)

Metal 1

3D view

Layout view

Source Drain

n+

P- substrate

Width



n-MOS technology layout and physical implementation (II)Step 3 – poly polygon as channel gate

Transistor channel length

Poly-silicon (conductive)3D viewLayout view

Source Drain

n+

Gate

P- substrate

Step 4 – active area

Active area for n-transistor (green)

n-MOS DONE

P- substrate

The MOS structure is automatically recognized by the active area rectangle

3D view Layout view

Source Drain

n+n+

Gate

WNMOS



p-MOS technology layout and physical implementation (III)Step 4 – p-MOS transistor

Active area for p-transistor (brown)

Note that the p-MOS width is increased

3D viewLayout view

WPMOS

Source Drain

Gate

p+ p+

Step 5 – n-well region

n-well

n-well

3D view Layout view

Source Drain

Gate

p+ p+

WPMOS

p-MOS DONE



CMOS technology layout and physical implementation (I)

M1

M2

p-MOS

n-MOSS

DG

S

D

VDD

GM1

M2

IN OUT

Schematic viewLayout view

Combine the n-MOS with p-MOS. Note the different sizes

WPMOS

WNMOS



CMOS technology layout and physical implementation (II)

S

DG

S

D

VDD

G

VGS

M1

M2

IN OUT

By poly connection (red)

By metal 1 connection (blue)


GND metal 1

(large to avoid a large ohmic voltage drop)

VDD metal 1(large to avoid a large ohmic voltage drop)



CMOS technology layout and physical implementation (III)

S

DG

S

DVDD

GM1

M2

IN OUT


By metal 1 (blue)

GND metal 1

VDD metal 1

By metal 1 (blue)

By metal

OUT

IN


GND

VDDOUT

n+ n+p+ p+n-wellp-substrate

n-MOS

p-MOS

Poly-gate (red)

3D View


Introduction to analog building blocks

S

DG

VGS

VDS

VDD

M1IN

OUT

RS

DG

VGS

VDS

VDD

M1IN

OUT

R

G

VGS

M1S

D

VDD

IN1

OUT

S

D

VGS

IN2

Common drainCommon source

Differential pair

M2

R R



Common source (single stage analog amplifier)

S

DG

VGS

VDS

VDD

M1IN

OUT

R

VIN

VOUT

VDD

VTH

MOS in saturation

VIN1

MOS OFF

MOS inLinear region

KVL:VOUT = VDD –R*ID

ID

S

DG

VDD

M1IN

OUTR

VIN is low < VTH

MOS is switch OFFID = 0 VOUT = VDD

S

DG

VDD

IN

OUTR

ron

VIN >> VTH MOS in linear

ron very low close a short

VOUT = VDD – gm * VIN * (R)

A

M1

VIN > VTH MOS in saturation

ID = gm* VIN

S

DG

VDD

IN

OUTRID

VOUT = - A * VINA

A B

B

C

C



Single stage amplifier

S

DG

VGS

VDS

VDD

M1IN

OUT

R

ID

VIN

VOUT VDD

VTH

MOS in saturation

MOS OFF

MOS inLinear region

time

time

Polarization voltage offset

Analog signal to be amplified

A* VIN

0

VBIAS


rM2

rM1

Gain = -gm1 * (rM1||rM2)

In many CMOS technologies, it is difficult to fabricate resistors with tightly-controlled values or a reasonable physical size.

It is desirable to replace the R with a MOS transistor (current mirror)

S

DG

VDD

M1IN

OUT

M2p-MOS current source for high ResistanceVbias

ID


Common drain (Source follower)Used as voltage buffer or level shifter

VOUT =~ VIN

Output follows the input

ID

S

DG

VGS

VDD

M1IN

OUT

R

RIN very high

ROUT very low

VIN

VOUT

VTH

MOS in saturation

VIN1

MOS OFF

VIN is low < VTH

MOS is switch OFFID = 0 VOUT = 0

S

DG

VGS

VDD

M1IN

OUT

R

S

DG

VGS

VDD

M1IN

OUT

R

VOUT = R * ID (KVL)

ID

VOUT = R * gm (VIN-VOUT)

A

A

B

B



Differential pair, why ? (Case 2)

S

DG

VDD

M1IN

OUT

R

Analog signal line Effect of supply noise on a single-ended amplifier

Noise from power supply

Solution ….

M2 INM1IN

VDD

VOUT = VOUT1 – VOUT2 Differential circuit

VOUT1 VOUT2



Differential pairVDD

M2VIN2

M1VIN1

VOUT1 VOUT2

ID

R RI1 I2

If VIN1–VIN2 << 0 M1 is OFF and M2 ON I1=0 and I2=ID => VOUT1 = VDD & VOUT2 = VDD - R*ID

M2VIN2

M1VIN1

VOUT1 VOUT2

ID

R RI2 = ID

A

M2VIN2

M1VIN1

VOUT1 VOUT2

ID

R RI1 = ID

If VIN1–VIN2 >> 0 M1 is ON and M2 OFF I1=0 and I2=ID => VOUT1 = VDD -R*ID & VOUT2 = VDD

BM2

VIN2M1

VIN1

VOUT1 VOUT2

ID

R RI1 I2

Middle VIN1–VIN2 M1 is ON and M2 ON ID = I1 + I2=> VOUT1 = VDD-R*I1 & VOUT2 = VDD-R*I2

C

VIN1 – VIN2

VOUTVDD

VDD – R*ID

VOUT1 VOUT2

A B

C



Differential pair (II)

Vout = Vout2 – Vout1 = gm1,2 * (R) * (VIN1-VIN2)

Gain


VDD

M2M1

VOUT1 VOUT2

ID

I1 I2

CMOS technology

R R

VIN1 – VIN2

VIN1 – VIN2

VOUT

VDD

A

B

VDD – R*ID

VOUT1 VOUT2

A

B A

B

Output

time time

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