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UWB Transceiver PrototypeIan ODonnell, Mike Chen,

Stanley Wang, Bob Brodersen

Berkeley Wireless Research CenterUniv. of California, Berkeley

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Flexibility for UWB Design Exploration

Different antennas (with impedance matching to the

LNA)

Variable transmit power

Variable pulse rates

Digital back-end will contain a programmable pulse-

matched filter

Adjustable data recovery/synchronization blocks

Independent synchronization and data PN sequences

I/O to send the A/D data directly to an external digital

backend (i.e. BEE) for more sophisticated signal

processing.

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UWB Transceiver Prototype

LNA

PULSE

GAIN and

FILTERING

A/DS/H

A/DS/H

A/DS/H

PMF

Data

Recovery

Synch

Detect

And

Tracking

CLK GENCONTROL

Goal: Tape-out Single-Chip Transceiver by end of Summer

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Pulse Transmitter

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Pulse Transmitter

Adjustable Slew Rate and Width Variable Magnitude Drive (I or V)

Ability to Drive High or Low Impedance

Digitally Programmable

PAM (Binary Antipodal), andPPM (2 to 4 Steps)

Desirable Functionality:

Implementation:

Differential Drive for PAMMultiplex DLL Clock Phases to Control

Width and for PPM

May Build Two Drivers and Selectively

Connect/Enable for Experimentation

TSLEW

TWIDTH

A

TRANSMIT PULSE

RECEIVE PULSE

time

time

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Flexible Antenna Driver

Put the antenna circuit model into circuit simulator

to design the driver

H-bridge configuration

Put them in parallel to make the driver flexible

EN0 EN0

EP0

Antenna Model

EP0

EN1

EN2

EP1

EP2

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Antenna-LNA Co-design

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Antenna/LNA Co-design

Impedance of the RX antenna seen by LNA is the same as

that of the TX antenna

Optimize LNA by putting the antenna model in front

Usually voltage-drive RX antennas prefer large ZLNA and

current-drive antennas prefer small ZLNA

LNA

ZLNAZANT

~

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Derive input impedance by simulations [U. Mass]

Voltage-drive antenna will be capacitor-dominant whilecurrent-drive antenna will be inductor-dominant

Equivalent Circuits for UWB Antennas

6cm Dipole Antenna

Input Impedance

Zant

Dipole Antenna

Rrad

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Example: Monopole RX Antennas

2cm monopole antenna with different loading

Larger ZLNA gives higher LNA input voltage

Mismatch due to scattering and near-zone field

The relative magnitudes are close

0 2 4 6 8 10 12

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time nS

Magn

itude(V)

0 2 4 6 8 10 12

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time (nS)

Magn

itude(V)

SPICEXFDTD

50K

5050

50K

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RX: LNA

Gain ~ 10 V/V over ~ 1GHz BW Noise Figure < 10dB (Not Critical In an

Interference Dominated Environment)

Differential Input

Handle Multiple Antennas (I.e. Current Loopand/or Dipole)

Switch Bias On/Off within TWINDOW Fast Overload Recovery (Track Full-

Scale 1GHz Sinusoid)

Desirable Functionality:

Implementation:

May Build Two Amplifiers and Selectively

Connect/Enable for Experimentation

-

+

-+

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CMOS Analog Frontend

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RX: Gain + Filtering

Minimum Gain = 1,000 Partition Gain/Stages for Minimum

Current Consumption

Capacitive Coupling Between Stages

(Null DC Offset) Switch Bias On/Off within TWINDOW Fast Overload Recovery (Track Full-

Scale 1GHz Sinusoid)

Additionally Include Filtering forFrequencies < 100MHz, > 1GHz

Last Stage Drives Sampling Switch

Load (could be ~100s fF)

Desirable Functionality:

ON

BIAS

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RX: A/D Comparator Requirement

1-Sigma VOFFSET for Fixed Tracking BW=1GHz

CLK

CLK

CSAMPLE

CSAMPLE

CSAMPLE

(fF)1 100010010

1

1000

100

10VOFFSET(mV

)

VOFFSET ~ 20mV

(w/ No Explicit

Cancellation) for

CSAMPLE > 10fF

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Clock Generation

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Pulse Reception

time

time

TSAMPLE

TWINDOW

TPULSE_REP

Parallel Sampling of Window of Time

Three Clocking Timescales:TSAMPLE (

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Timing Generation

For Lower Power: Base System Clock on TWINDOWTSAMPLE Derived from DLL

TPULSE_REP = TWINDOW / N

DIVIDER

DIVIDER

DLL

DIVIDER

DLL

PLL

TSAMPLE

TWINDOW

TPULSE_REP

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RX: Clock Generation

VARIABLE DELAY LINE

OSCILLATOR

CHARGE

PUMP

&

LOOP

FILTER

PHASE

DETECTOR

EXTERNAL

CRYSTAL

TSAMPLE

= TWINDOW

/N

TWINDOW

BUFFER

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Overview of UWB Baseband

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Baseband Overview

CLKA

PMF

Coef

S

/

P 2568

128

PN correlator 1

PN correlator 2

PN correlator 128

fchip

PN GenCLKC fchip

Peak

Det

Data

Recover

(soft/hard)

Controllogic

Correlation_Block

Symbol

Strobe

Data

PN

Correlator

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Acquisition Mode

PN Correlator 1

PN Correlator 2

PN Correlator 128

ADC

Searching for the peak at the ouput of correlators

Threshold

P

M

F

From PN generator

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Tracking Mode

PN correlator 1

PN correlator 2

PN correlator N

Abs

Max

Value

Max Adr

Max Value

Data Recovery

1. Hard decision (symbol detection).

2. Soft Sequence detection, such asViterbi decoding.

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