D
WIDEBAND
MM
TUTORE
CHIAR.MO
COORDINATORE
CHIAR.MO
UNIVERSITÀ DEGLI STUDI DI PAVIA
FACOLTÀ DI INGEGNERIA
Dipartimento di Elettronica
DOTTORATO DI RICERCA IN INGEGNERIA ELETTRONICA,
INFORMATICA ED ELETTRICA
XXI CICLO
IDEBAND FRONT – ENDS FOR UWB AND
MM-WAVE LOW – POWER WIRELESS
COMMUNICATIONS
UTORE:
MO PROF. FRANCESCO SVELTO
OORDINATORE:
MO PROF. GIUSEPPE CONCIAURO
TESI DI DOTTORATO DI
MARCO S
1
AND
OTTORATO DI
SOSIO
2
3
“Climb on the back and we’ll go for a ride in the sky”
Paul McCartney, Jet
from the Album “Band on the run” (1973)
4
Acknowledgement
5
Acknowledgement
First of all I wish to thank my tutor Prof. Francesco “Frank”
Svelto, for his stimulating suggestions and his perseverance in
encouraging us.
I’m particularly grateful to all my colleagues that were with me
over these three years as a Ph.D. student:
− Brando, the big scientist who introduced me to the RF
microelectronic world.
− KBeppe, the man who introduced me to the wonderful
world of Linux.
− Mazza, for all his experience and precious hints about RF
and also about Modena slang.
− Stefano and Federico, the other two members of the
“Houston Mission Control Center”, who shared with me
delights and sorrows of this Ph.D. period.
− Tony, the other guy from Valtellina, for all his precious
advices in these University years.
− Vahid, the best (and only!) middle east engineer I know,
for his many real questions and his help during many
measurement campaigns!
Acknowledgement
6
I cannot forget people from ST:
− Enrico, one of the most patient person I’ve ever met, for
his help (technical and not) during my Ph.D. period and
for having let me know Idrolitina and Ispettore Coliandro.
− Repox, the well – calibrated man, for having shared with
me the exciting experience of the first “probe landings”:
the very beginning of the mm – wave experience in Pavia!
− Guerma, the best implementing engineer in the world, for
his many ideas and fruitful discussions; I will never forget
the “chair diving” brainstorming.
Index
7
Index
Introduction: ........................................................................ 9
I.1 Sub – Harmonic mixing ............................................ 10
Chapter 1: UWB and mm – Waves Systems .......................... 17
1.1 Why UWB and mm – Waves .................................. 18
1.2 The Ultra Wide Band (UWB) system ...................... 23
1.3 Applications at mm – waves .................................. 26
1.3.1 Automotive Radar ................................................. 28
1.4 Why Silicon CMOS .................................................. 30
1.5 Future Trends ......................................................... 35
Referenecs ............................................................. 36
Chapter 2: A Reconfigurable Demodulator with 3GHz – 5GHz
Agile Synthesizer for 9-band WiMedia UWB
in 65nm CMOS ...................................................................... 37
2.1 Introduction ........................................................... 38
2.2 Reconfigurable quadrature passive mixer ............. 40
2.3 Frequency synthesis ............................................... 42
2.4 Layout and Experiments ........................................ 46
References ............................................................. 54
Chapter 3: A 24GHz Sub-harmonic Receiver front-end with
integrated multi-phase LO generation in 65nm CMOS .......... 55
3.1 Introduction ........................................................... 56
3.2 Front – End Architecture ........................................ 57
3.3 Frequency Synthesis .............................................. 58
Index
8
3.4 LNA Design ............................................................. 60
3.5 Mixer and Baseband Design .................................. 62
3.6 Layout and Experiments ........................................ 64
References ............................................................. 68
Appendix A: A 750mV Fully Integrated Direct Conversion
Receiver Front-End for GSM in 90nm CMOS ......................... 69
A.1 Introduction ........................................................... 70
A.2 Low voltage highly linear direct downconverters.. 73
A.2.1 Effects of transconductor IM2 on
downconverter IIP2 ........................................................77
A.2.2 Direct downconverter with input – output
common mode feedback ................................................82
A.3 750mV Front – End ................................................ 86
A.4 Layout and Experiments ........................................ 91
A.5 Conclusions ............................................................ 100
References ............................................................. 101
Bibliography ......................................................................... 105
Introduction
9
Introduction
The cellular phone market is and will remain for long the
stronghold in semiconductor industry among wireless
communications.
However, the growing demand for larger bandwidth
motivates integrated circuits to move toward higher frequencies.
While the lower frequency bands have been extensively
explored for various wireless applications, there is an obviously
an inherent bandwidth advantage in exploring higher (or wider)
frequency ranges. This mean the possibility of higher data rate
or, for a fixed data rate, longer distances communications.
Silicon – based technologies, in particular CMOS, are good
candidates for highly integrated and low cost solutions at such
frequencies, as will be shown in this PhD. Thesis.
High data – rate UWB (Ultra Wide Band) systems in the
3.1 – 10.6 GHz range address the task of home/office cable
replacement, enabling the growth of short range high speed –
Introduction
10
links. Wireless monitors, direct printing of digital pictures from
cameras end quick transfer of large files among cell phone
handsets are just a few examples in the ever – growing scenario
of multimedia.
Moreover, an intense research activity toward the
realization of highly integrated solutions in silicon processes at
Ka band and mm – wave frequencies is presently under – way,
after the Federal Communications Committee has granted
unlicensed bands around 24 GHz, 60 GHz and 77 GHz for several
wireless applications.
One big issue for UWB systems is that reference
frequency generation in wide – band CMOS systems is usually
power hungry; another big issue, in particular at Ka band (24
GHz), is that variable capacitors, used as tuning elements in
voltage controlled oscillators, present poor quality factors for a
given tuning range and dividers, used in the PLL, are also power
hungry.
A possible solution addressing all the problems explained
above is the usage of sub – harmonic mixing techniques.
I.1 Sub – harmonic mixing
Mainly two different techniques are known for sub –
harmonic down conversion: 1) exploiting the non linear behavior
Introduction
11
of active devices to produce higher harmonics of the LO
waveform and 2) multiplying the received signal with a number
of uniformly spaced LO phases. While the former determines a
penalty in conversion gain and noise, the latter displays
performances similar to the conventional Gilbert – Cell at the
expense of a more complex LO generation circuit.
The basic idea for multi – phase half – harmonic mixing is
the multiplication of the RF input signal times a LO and a π/2
phase shifted replica of the same square wave reference, as
shown in figure I.1.
Figure I.1 Basic idea of sub – harmonic mixing
Introduction
12
In fact, multiplication by two square – wave LOs, π/2
phased apart, represented in figure I.2, corresponds to
multiplication by one single square – wave reference at twice the
frequency, according to:
× = 2 (I.1)
where sign[x] = 1 for x>0 and sign[x] = -1 for x<0.
Figure I.2 LO waveforms and LO equivalent waveform
The input signal at frequency ωin is then downconverted
at ωin -2ωref with a reference signal at ωref.
Introduction
13
From equation I.1 , we observe that if the two half
frequency signals are shifted by π/4 the resulting equivalent
reference oscillator is π/2 shifted:
+ 4 × +
4 =
= 2 (I.2)
Quadrature down – conversion can thus be performed by
means of a pair of half – harmonic mixers, provided the driving
signals in each switching stage follows the phase sequence
reported in equations I.1 and I.2.
A simplified schematic of the CMOS half – harmonic
quadrature demodulator architecture used in this work is shown
in figure I.3.
Introduction
14
Figure I.3 Simplified schematic of a quadrature Sub – Harmonic downconverter
The mixer core is made of two cascade double balanced
differential pairs, driven by π/2 phase shifted LO signals. For low
voltage operation, the mixer is passive i.e. mosfets do not carry
static current and are operated as switches. For better I&Q
matching, the same high frequency current feeds both I & Q
demodulators. A differential pair, AC coupled to the mixers, is
used to drive the switching core. Furthermore, assuming a single
Introduction
15
– ended LNA precedes the stage, the transconductor also
performs single ended to differential conversion. A trans –
impedance amplifier with the input device in common – gate
configuration loads the mixer. For high frequency operation a
low impedance loading is preferred over the high impedance
alternative, showing higher immunity to signal loss due to device
parasitic capacitances.
In Chapter 1 a general overview and some key features
about Ultra Wide Band and mm – wave systems will be
discussed. The reasons behind the choice of moving to higher
and wider frequency bands will be deeply investigated.
In Chapter 2 a reconfigurable demodulator for UWB
systems will be discussed. In this approach the sub – harmonic
architecture is used in a reconfigurable fashion allowing the local
oscillator to cover only a fraction of the RF frequency range, with
great advantages in power consumption.
In Chapter 3 a complete Front – End working at Ka band
(24 GHz) is addressed. At such a high frequency particular
attention should be given to the parasitic components
(capacitive, resistive and inductive), in particular for the single –
ended LNA. Extensive full – wave simulations have been
performed. The sub – harmonic architecture, with a VCO running
Introduction
16
at half – frequency, allows us to save power and to get a better
performance of variable capacitors.
In Appendix A, on the other hand, a narrow – band
approach for cellular phones is presented.
A fully integrated Direct Conversion Front – End for GMS,
preparatory to higher frequency low power applications, is
presented. This front end can work with a voltage supply as low
as 750mV thanks to a common mode feedback in the mixer that
enhances its IIP2 performance.
Chapter 1
17
1111
UWB and mm – Waves systems
In the last few years the fast growth of wireless data
systems such as WiFi spurred significant research into
development of new architectures for radio transceivers that can
deliver very high data rates over short ranges, particularly for
video and personal area networks. The fact that now users own
gigabytes of personal data and they use mobile devices as a
personal storage make the exchange and transfer of contents a
necessity; moreover the introduction in the market of handheld
video devices, HDTV and flat screen televisions has boosted the
demand for a technology that enables high speed wireless video
transmission. Considering these aspects, a “free” and fast local
connectivity is required. In this scenario UWB and mm-wave
Chapter 1
18
silicon technology have been addressed as possible approaches
to this necessity.
UWB is a potential solution, as will be shown in chapter 2,
but it has some shortcomings including problems with
interference (such as WiFi) and limited data rate. Moreover, the
very limited transmit power (about 0 dBm) means that
bandwidth has to be traded to overcome the limited SNR. More
promising solutions seem possible using the mm-wave bands (24
GHz and 60 GHz), that offer nearly the same amount of spectrum
(7 GHz) but less crowded, and up to 40 dBm of transmit power.
At first glance, it seems unbelievable that such high
frequencies could be handled efficiently with CMOS silicon
technology, worse yet with bulk CMOS. However, as will be
shown in this work, the combination of CMOS scaling (i.e.
increased transistor speed) and new design methodologies (i.e.
the extensive usage of distributed components and full wave
analysis) can be a very good and effective approach to the
problem.
1.1 Why UWB and mm - Waves
From Shannon’s theorem [1.1]:
(1.1)
( )SNR1logBWC 2 +⋅=
Chapter 1
19
where C is the maximum data rate of a communication channel
(i.e. channel capacity), BW is the Bandwidth of the channel, and
SNR is the Signal – to – Noise ratio of the information carried.
From this simple equation we can easily gain that one
way to increase the communication speed (data rate) is by
means of more bandwidth. This is the basic concept behind the
choice to allocate the wide bandwidth of 7 GHz for UWB
systems, from 3 to 10 GHz.
The information is usually modulated around a carrier
frequency: therefore more bandwidth is available around higher
carrier frequencies. This is the main reason that drives the
research on mm – wave systems. Moving up to higher
frequencies also provides natural isolation from fast switching
digital circuitry, today already operating at several GHz clock
speed. Furthermore, the huge bandwidth at mm – wave
frequencies allows us to use low order modulation schemes for
the communication; in the low GHz regime, on the other hand,
the high data rate applications require sophisticated signal
modulations, often implying stringent demands on the
specifications of the RF analog blocks, as will be shown in
Appendix A. A lot of power has to be consumed in the baseband
of these systems to provide advanced functions like FFT and
equalization. What is somehow amusing is that the above
solutions can end up consuming more power than mm – wave
Chapter 1
20
solutions, despite the higher power consumption of the analog
front – end at mm – wave frequencies.
For all these reasons the Federal Communication
Commission (FCC) [1.2] has allocated several bands at mm –
wave frequencies for high data rate wireless communications. In
figure 1.1 the UWB spectrum is shown, together with the 22 – 29
GHz frequency band allocated for short – range radar
applications such as park assist, stop – and – go and blind spot
detection; a Front – End for this band will be discussed in
chapter 3. Moreover the so – called “60 GHz band” (57 – 64
GHz), that has generated much interest from industry and the
venture community, is shown. The FCC allocated also some other
mm – wave bands, like the licensed E – band for fixed point – to
– point communications (71 – 76 GHz, 81 – 86 GHz and 92 – 95
GHz) and the 76 – 77 GHz band for “adaptive cruise control”
radars, not shown in the picture.
Figure 1.1 UWB band and some FCC – allocated mm – wave Bands in U.S.A.
Chapter 1
21
Unfortunately, the signal at higher carrier frequencies
experiences more attenuation due to the following reasons:
• Antenna size is inversely proportional to carrier
frequency: the higher the frequency the smaller
the antenna and this means less collected power.
• Higher absorption of air is of serious concern at
mm – wave frequencies.
Higher attenuation means lower SNR and so reduced data
rate in the communication system (or shorter distance for a
given SNR). Also interferers could be a problem, because they
lower the SNR too; however, the larger attenuation at mm –
wave frequency in this case is helpful to improve spatial isolation
between different radios and also the multi path fading effect is
mitigated because of higher air absorption. Furthermore, the
high oxygen absorption at 60 GHz is the main reason for the FCC
to allow for up to 40 dBm EIRP transmit power, which makes
possible multi – Gb/s wireless transmissions over typical indoor
distances.
To increase the SNR (hence the data rate) in a
communication system, many different solutions have been
employed: complex modulations, codes and diversity schemes.
However, the most suitable solution for mm - wave applications
Chapter 1
22
seems to be the phased arrays: spatially separated antennas can
be used to increase the received SNR, leading to a higher data
rate. They also have a beneficial directivity effect focusing the
signal energy into a narrow beam and placing nulls in other
(undesired) directions. This approach is very suitable for radar
and imaging applications, moreover the inverse proportionality
between frequency and antenna size allow us to make arrays
with more elements (considering a fixed area) if compared to
lower frequency applications.
In figure 1.2 there is an example of a phased array
transceiver: as can be understood from the picture, all the
advantages explained above should be considered taking also
into account the drawbacks related to the increase of silicon
area and the increase of power, because of multiple
instantiations of transmitters and receivers on the same die.
Chapter 1
23
Figure 1.2 A phased array transceiver
However, we should also consider that, due to the small
wave – lengths, antenna arrays can be realized in very small
area: this enables the possibility of on – chip antennas.
Moreover, automatic power control can be realized by simply
turning off some of the transmitter / receiver paths when not
necessary. So what we have to pay is reasonable if compared to
the increased link margin, that means stronger communication
performance.
1.2 The Ultra – Wideband (UWB) system
In 2002, the FCC [1.2] defined as Ultra – Wideband any
signal occupying more than 500 MHz frequency and having an
average power spectral density limit of -41.3 dBm/MHz, in the
3.1 – 10.6 GHz range.
Chapter 1
24
This unlicensed band is intended to enable several
applications: ground penetrating radars, imaging and
surveillance systems, safety / health monitoring are just a few
examples. Other applications in the ever – growing scenario of
multimedia are of great interest: home / office cable –
replacement with high speed wireless links, like wireless
monitors, direct printing of digital pictures from cameras and
quick transfer of large files among cell phone handsets are other
examples. The very low power spectral density, due to wide
band, and the flexible characteristics of this communication
system are the key points for immunity to interferes and
propagation issues. Benefits in terms of relaxed linearity
requirements and filters selectivity allow low power, fully
integrated, inexpensive solutions.
In this work (chapter 2) the UWB proposal exploiting the
MB – OFDM (Multi – Band Orthogonal Frequency Division
Multiplexing) modulation scheme will be considered, allowing a
variable throughput from 53.3 to 480 Mbit/s.
Chapter 1
25
Figure 1.3 Channels allocation for MB – OFDM UWB
The 3.1 – 10.6 GHz band is divided in 14 channels
organized in five groups, as depicted in figure 1.3. The center
frequency of each channel is given by the following equation:
= 2904 + 528! "#$%& ! = 1,2, … , 14 (1.2)
The allocation of the spectrum is intended for progressive
expansion of the communication capability. First generation of
UWB devices will use only a few channels (channels of group #1),
while successive generations will spread information over more
channels. Notice that due to the frequency hopping scheme and
the average power spectral density limit, this translates in a
higher transmitted power integrated in the whole band. For this
reason the use of a higher number of channels will extend the
communication range, or will improve the data – rate for a given
Chapter 1
26
distance. In this direction, a UWB demodulator tailored to UWB
groups 1,3,4 will be presented in chapter 2.
1.3 Applications at mm - waves
There are many new opportunities for circuits operating
at mm – wave frequencies. Above all, wireless communications
are always the key target. The larger bandwidth available at
higher carrier frequencies allows us to increase the
communication speed (data rate) for a given distance or, on the
other hand, increase the communication distance for a fixed
data rate.
Moreover, new potential applications, for example,
include mm – wave imaging and sub – THz chemical detectors,
with applications in chemistry, medicine, physics, astronomy,
and security. Figure 1.4 shows the propagation attenuation
characteristic versus frequency for earth atmosphere under
various conditions [1.3].
Chapter 1
27
Figure 1.4 Attenuation characteristic [dB/km] of air versus frequency under various conditions [1.3]
Looking at this diagram, we can understand that there are
“windows” of opportunities where the attenuation is either
minimal or maximal: for example, the 60 GHz band is suitable for
short range networks with good spatial isolation because of high
oxygen absorption at 60 GHz, whereas the 90 GHz band is
suitable for long range imaging.
In the following we will focus the attention on a particular
application specifically addressed in this work (chapter 3).
Chapter 1
28
1.3.1 Automotive Radar
The key development of automotive radars has been the
dramatic reduction in area, cost and power for such a system.
Until now, only luxury automobiles were equipped with mm –
wave radars (with compound semiconductor technologies), but
this situation is going to change soon: it’s a matter of time
before CMOS technology become industry standard for also this
field of applications. Figure 1.5 shows a possible future road
environment with many driving assist features.
Figure 1.5 Hypothetic future road environment with many driving assist features
Chapter 1
29
Promising technologies are radars at 24 and 77 GHz.
Radar is an all – weather sensor with approximately 5 cm
resolution that operates in real time. The scanning RF signal,
usually a pulse – shaped signal, is transmitted toward the target
of interest. Information regarding shape, distance and speed of
the target is embedded in the arrival time and shape of the
reflected pulse.
The FCC has allocated the 22 – 29 GHz band for short
range automotive radar applications and the 76 – 77 GHz band
for long range (100m) automatic cruise control automotive radar
application [1.2]. FCC allowed also using the ultra wideband
(UWB) technology to achieve a higher resolution for short range
vehicular sensing applications like blind spot detection and side
(or rear) impact sensing.
The rate of successful detections and false alarms is a
critical system metric for radars; it becomes more and more
important considering that automotive radars are related to
road safety. Once again, to reduce the rate of false alarms,
phased arrays are a good solution because they reduce the
undesired effect of multiple reflections and interferences while
allowing for full spatial coverage; moreover, also the SNR is
enhanced.
Chapter 1
30
1.4 Why Silicon CMOS
Silicon is not the obvious choice for UWB and mm – wave
systems. Many alternatives are possible: GaAs, MESFETs,
PHEMT, InP, HEMT, GaAs MHEMT, GaAs HBT, InP HBT. While
these exotic technologies offer good performances at high
frequencies of operation, they are very expensive and have low
manufacturing yields. Therefore we can say that, as for RF
applications in the low GHz regime, other technologies will soon
be displaced by the lower – cost and higher – yield silicon.
Moreover, these exotic processes are not expected to
scale (in size and in cost) as fast as silicon CMOS. As a matter of
fact, silicon enjoys steady scaling, mainly driven by the digital
aim to reduce the cost per function. Transistors became small
enough, and consequently fast enough, to operate at
frequencies as high as 60 GHz. Now mm – wave silicon circuits
have been widely demonstrated starting with the 130 nm
technology node. Despite many dire predictions about CMOS
scaling, the scaling has continued down to the 45 nm technology
node and it’s still going on. It should be noted, however, that
scaling alone is not enough to justify this increased speed: new
design methodologies are mandatory to increase the operating
frequency by a factor of 10 (for example from 6 to 60 GHz) while
Chapter 1
31
the process fT has only doubled in the last few technology steps
(figure 1.6.a and figure 1.6.b ) [1.4].
(a)
0
20
40
60
80
100
120
140
2000 2005 2010 2015 2020 2025
Year
Lg [nm]
Chapter 1
32
(b)
(c)
Figure 1.6 Channel length, transition frequency and Vdd trends according to ITRS [1.4]
0
100
200
300
400
500
600
700
800
900
1000
2000 2005 2010 2015 2020 2025
Year
fT [GHz]
0
0,2
0,4
0,6
0,8
1
1,2
1,4
2000 2005 2010 2015 2020 2025
Year
Vdd [V]
Chapter 1
33
These “new design methodologies” are somehow a
revolution of RF design techniques. RF designers, used to lower
frequencies designs, are expert in an approach based on
compact models mainly SPICE – based. On the other hand
microwave designers are expert in full – wave simulations for
distributed analysis and s – parameter characterization based on
extensive measurements. Mm – wave design means using both
approaches, trying to understand step by step which is the most
appropriate, as will be shown in chapter 3.
Anyhow at the end of this paragraph it should be pointed
out that when working with ultra – scaled devices we have to
consider some inherent drawbacks: with technology scaling the
intrinsic gain of the mosfet is getting lower and lower (gm/g0 ≈10
with 65nm technology) and extremely low supply voltages
(figure 1.6.c) mean severe limitations in the achievable voltage
swing. Moreover, the conductive bulk substrate means higher
losses in passive components such as inductors and transmission
lines.
Besides, there’s no inherent area advantage in using
scaled technology nodes: as a matter of fact, a common mm –
wave chip is dominated by passive devices and not by active
devices, as can be seen in figure 1.7; despite this, there is still
motivation to continue to use newer scaled technology since
Chapter 1
34
smaller transistors will provide higher performances at constant
or even lower power levels.
Figure 1.7 A 24 GHz LNA. Active Area is only a very small part of the total area
Chapter 1
35
1.5 Future trends
What makes mm – wave silicon attractive is the higher
level of integration offered with a high yield, that means lower
cost systems. In the last few years, industries and universities
started their own investigation in the development of higher
frequency systems (UWB, 24GHz, 60 GHz and over). Many
results are now available from different sources, as will be
discussed more in detail further on in this work.
Anyhow a few trends can be predicted for the near
future: the main goal is the realization of a complete transceiver
at 60 GHz using a standard bulk CMOS technology. Beam –
forming CMOS integrated arrays are also a topic of great
interest. Moreover, the issues of packaging and the antenna
integration problem is an open field of research for mm – wave
designers.
Chapter 1
36
References
[1.1] C. Shannon “A Mathematical Theory of Communication”,
The Bell System Technical Journal, vol. 27, July – October
1948
[1.2] Title 47 of the Code of Federal Regulations (47 CFR), Part
15, Federal Communications Commission, July 2008
[1.3] L. Yujiri, M. Shoucri, P. Moffa, “Passive mm – Wave
Imaging”, IEEE Microwave Magazine, vol. 4, issue 3, pp. 39
- 50, September 2003
[1.4] International Technology Roadmap for Semiconductors,
http://www.itrs.net, Reports from 2000 to 2007
Chapter 2
37
2222
A Reconfigurable Demodulator
with 3GHz – 5GHz Agile Synthesizer
for 9-band WiMedia UWB in 65nm
CMOS
Reference frequency generation in wide-band CMOS
receivers is usually power and area hungry. In this work, a
demodulator is reconfigured between fundamental and sub-
harmonic operation modes, requiring a reference covering less
than 1/3 the RF bandwidth. The realized chip, tailored to UWB
groups 1,3,4, includes a 4 phase ring oscillator injection locked by
Chapter 2
38
LC PLLs, and quadrature mixers followed by trans-impedance
amplifiers. The synthesizer consumes 43mW only.
2.1 Introduction
Receiver ICs realized in CMOS technology leverage the
narrow-band nature of wireless standards to meet specifications
at low power levels. The advent of wide-band systems, e.g.
software defined radios and UWB technology, is determining
new emphasis on innovative techniques for key RF circuit blocks,
synthesizers in particular [2.1-2.4]. Ring oscillator based
solutions lend themselves to wide-band operation but the signal
quality at moderate consumption is usually inadequate, LC-tank
based oscillators do not cover the range requiring multiple VCOs.
Sum and difference frequencies can be generated from a single
VCO and its divided replica by means of SSB mixers.
Unfortunately, also significant spurious tones are created due to
non-idealities in the mixers. As an alternative, RF signals
belonging to a wide-frequency range can be demodulated in a
single receiver chain by means of a down-converter,
reconfigured between conventional and sub-harmonic operation
modes. In this way, the local oscillator is required to cover only a
fraction of the frequency range, demodulating the lower portion
Chapter 2
39
in conventional mode and the upper in sub-harmonic mode. For
sub-harmonic down-conversion, 4 differential phases of the
same reference are needed but the advantage of lower
frequency range of operation outweighs the added complexity.
In this work, we propose a 65nm CMOS reconfigurable
direct-conversion receiver, tailored to WiMedia UWB (band
groups #1,3,4) including frequency synthesizer, mixer and base-
band first stage. Experiments show a robust operation while the
synthesizer requires 43mW only (lowest to authors’ knowledge).
Chapter 2
40
2.2 Reconfigurable quadrature passive mixer
Figure 2.1 Reconfigurable Quadrature passive mixer
Figure 2.1 shows the diagram of the quadrature passive
mixer, core of the proposed demodulator. The input RF current
is down-converted to DC by means of two stacked double
balanced switching stages. Differential reference signals driving
each stage are provided according to the phase sequence
Chapter 2
41
reported in the figure. When either of the two stages is set to a
constant biasing while the other switches at the LO frequency,
the down-converter operates in conventional mode, and the
output frequency equals ωRF−ωLO. When the two stages are
switched at the same LO frequency by reference signals phase
shifted by 90°, the output frequency equals ωRF−2ωLO. The
multiple phase reference is generated by a ring oscillator and a
phase selector reconfigures the mixer for either operation mode.
Chapter 2
42
2.3 Frequency synthesis
Figure 2.2 Block diagram of the I & Q demodulator and frequency synthesizer
Figure 2.2 shows the block diagram of the proposed
solution. In order to demodulate UWB groups 1,3,4 the required
frequency range for the demodulator and the LO generator are
3.1GHz to 9.5GHz and 3.3GHz to 4.62 GHz, respectively. To
provide a spectral pure, low phase noise reference, the ring
Chapter 2
43
oscillator is injection locked by a LC VCO based PLL. Due to the
specified fast frequency hopping within a 3 bands group, the
system is intended to operate with 3 separate PLLs each
dedicated to a single band. In the present implementation, only
two have been integrated while the third input provides a
reference generated off-chip for testing purposes. When locked,
the output signals of the ring oscillators maintain the desired
relative phase difference of exactly 45° only if the free-run
frequency is the same as the locking frequency. Digital
calibration of the oscillation frequency is therefore included,
together with a set of registers to store the calibration words for
each channel frequency. The signal determining which of the
three PLLs locks the ring also selects the corresponding
calibration word.
Chapter 2
44
Figure 2.3 Ring oscillator
The detailed schematic of the ring oscillator is drawn in
figure 2.3. Each delay cell is made of a differential pair and binary
weighted switched pMOS loads, working in the linear region.
Eight control bits allow achieving a frequency resolution of less
than 20MHz, fine enough to keep the deviation from nominal
phase difference to less than 0.5° in locked condition. To
maintain a constant output swing at different frequency, current
consumption is automatically regulated by a replica biasing
circuit. The locking signal is provided to the ring by means of an
additional differential pair shunting a delay cell. Locking
Chapter 2
45
bandwidth is set by its tail current (Iinj). The larger Iinj, the larger
the locking bandwidth, i.e. the ring phase noise suppression, but
the less the phase accuracy due to the asymmetries introduced
in the loop. Iinj is set for a locking bandwidth of 1.5GHz as the
best compromise. The on-chip PLLs use an integer-N architecture
employing a reference frequency of 66MHz. LC-VCOs cover the
required frequency range in 8 overlapping bands. Frequency
dividers are implemented with a divide-by-two CML stage
followed by a pulse-swallow counter. Maximum current
consumption is 5mA for each PLL. The front-end RF
transconductor is implemented by means of a differential pair
biased with a center-tapped choke inductor. Schematic of the
base-band trans-impedance amplifier is shown in figure 2.4 and
it is made of a unity current gain common gate stage with a
differential output load, determining a first order filter.
Chapter 2
46
Figure 2.4 Trans – Impedance Amplifier
2.4 Layout and Experiments
The die micrograph of the circuit, fabricated in the
STMicroelectronics 65nm CMOS process, is shown in figure 2.5.
The chip draws 66mA from 1.2V supply. The ring oscillator free
run frequency is digitally programmable between 3GHz and
5.6GHz. During characterization the ring is locked by the PLLs.
Frequency hopping within the same group sets 9.5ns as
maximum allowed band switching time, determined by
multiplexer delay plus ring locking transient in our solution. A
settling time of less than 6ns has been measured switching the
LO frequency between 3.432GHz and 3.960GHz and down-
Vdd
Downconverted
current signal
Output buffers
TRANS – IMPEDANCE
AMPLIFIER
Chapter 2
47
converting a 3.372GHz RF signal to base-band, as shown in
Figure 2.6.
Figure 2.5 Chip microphotograph
Chapter 2
48
Figure 2.6 Demodulator settling time. The LO frequency is switched between 3.432GHz and 3.960GHz while a 3.372GHz RF signal is down-converted to base-band
Chapter 2
The phase noise at 10MHz
dBc/Hz
noise is less than
Figure 2.curve) and injection
Keeping low spur levels to avoid down
undesired interferers is key. Figure
spectrum when the ring is locked to 3.960
and the external PLL are 528MHz apart on the
The phase noise at 10MHz offset from 3.96GHz is
, determined by the injecting LC PLL. Integrated phase
noise is less than 1.7°. Figure 2.7 plots the phase noise results.
Figure 2.7 Phase Noise plots : ring oscillator in free running curve) and injection-locked by the on-chip LC-PLL (bottom curve).
Keeping low spur levels to avoid down-conversion of
undesired interferers is key. Figure 2.8 shows the output
spectrum when the ring is locked to 3.960GHz by PLL2 while
and the external PLL are 528MHz apart on the two frequency
49
is -128
Integrated phase
7°. Figure 2.7 plots the phase noise results.
in free running (top
conversion of
shows the output
2 while PLL1
two frequency
Chapter 2
50
sides. The largest spurs, due to two sides PLLs, are -43dBc. Spurs
around the synthesized frequency are due to the reference and
its harmonics, while no spurs are present in the 5GHz-6GHz
WLAN range.
Chapter 2
51
Figure 2.8 Local Oscillator output spectrum when PLL2 locks the ring at 3.96GHz while PLL1 and the external PLL are 528MHz apart. Spurs around 8GHz are 2
nd harmonics generated by the single-ended
measurement buffers.
The demodulator gain is 10dB both in fundamental and
sub-harmonic operation modes, and the output frequency pole
is at 300 MHz. A sudden decrease of 4 dB is observed in the last
bands (8.7GHz-9.5GHz), attributed to the PCB frequency
response.
Figure 2.9 show the I&Q phase error. The error from
quadrature of I & Q down-converted signals is less than 2°.
Chapter 2
52
Figure 2.9 Measured I & Q waveforms downconverted at 10MHz IF with the mixers operating in Fundamental mode (top plot) and SubHarmonic mode (bottom plot). I&Q phase error in worst case, measured among several samples, is around 2°.
Input referred noise voltage spectral density is 2.3
nV/√Hz. Out of band linearity tests have been performed: 1dBV
IIV3 (11dBm IIP3 on 50Ω), with tones at 5.2GHz and 5.8GHz, and
Chapter 2
30dBV IIV2 (40dBm IIP2 on 50
5.2GHz, have been derived. Table
results.
30dBV IIV2 (40dBm IIP2 on 50Ω), with tones at 1.9GHz and
5.2GHz, have been derived. Table 2.I summarizes measured
results.
Table 2.I
53
), with tones at 1.9GHz and
I summarizes measured
Chapter 2
54
References
[2.1] J. Lee, “A 3 to 8GHz Fast Hopping Frequency Synthesizer in
0.18 µm CMOS Technology”, IEEE Journal of Solid State
Circuits, Vol. 41, no.3, pp. 566-573, March 2006.
[2.2] T.-C.Lee, and K.-J.Hsiao, “The Design and analysis of a DLL
Based Frequency Synthesizer for UWB Applications” IEEE
Journal of Solid State Circuits, Vol. 41, no.6, pp. 1545-
1552, June 2006.
[2.3] S.Dal Toso, A.Bevilacqua, M.Tiebout, S.Marsili, C.Sandner,
A.Gerosa, A.Neviani, “UWB Fast Hopping Frequency
Generation Based on Sub Harmonic Injection Locking”
IEEE International Solid State Circuits Conference, Digest of
Technical Papers, pp. 124-125, Feb. 2008.
[2.4] J.R.Bergervoet, K.S.Harish, S.Lee, D.Leenaerts, R. van de
Beek, G. van der Weide, R.Roovers, “A WiMedia-
Compliant UWB Transceiver in 65nm CMOS” IEEE
International Solid State Circuits Conference, Digest of
Technical Papers, pp. 112-113, Feb. 2007.
Chapter 3
55
3333
A 24GHz Sub-harmonic
Receiver front-end with integrated
multi-phase LO generation in 65nm
CMOS
A sub-harmonic architecture for wireless signal processing
at Ka band is proposed resulting in IC power saving because the
LO circuits operate at half frequency and no IF stage is necessary.
A 65nm CMOS prototype, including High Frequency front-end,
base-band amplifier and multi-phase VCO and dividers, shows:
Chapter 3
56
31.5dB gain, 6.5dB NF, -17dBm IIP3, -90dBm LO re-irradiation at
24GHz, while consuming 92mW.
3.1 Introduction
The outcome of the recent research effort in the design of
Ka band and mm-wave silicon ICs is motivating several industrial
projects toward the realization of chipsets for broad-band
communications and automotive cruise control. Standard CMOS
proves sufficient performances up to 60GHz range and examples
of operating blocks even beyond have been presented [3.1-3.2].
Still, the choice of the receiver architecture entails several
peculiar considerations in order to achieve a robust, low-power
solution. Frequency conversion to DC or close has been
privileged in most cases at RF to allow a high integration level in
CMOS. On the other hand, at higher frequency, it is desirable to
synthesize a reference frequency lower than received frequency
in order to save power both in the VCO and dividers. A
multiplier, following the synthesizer, can be adopted but this
prevents I & Q down-conversion, mandating a further IF
processing stage. Moreover, leakage between signal and LO
ports, exacerbated at high frequency, determines offset, inter-
modulation distortion and LO re-irradiation, deleterious for
Chapter 3
example in automotive radars. In this scenario, we propose a
half-harmonic 24GHz
with integrated multi
Experiments show
compact (2.1mm
authors’ knowledge) in ultra scaled
3.2 Front
Figure
Figure 3.
example in automotive radars. In this scenario, we propose a
harmonic 24GHz direct conversion I & Q receiver front
with integrated multi-phase LO generation in 65nm CMOS.
Experiments show that adequate performances are achieved in a
compact (2.1mm2), low power solution (first below 100mW, to
authors’ knowledge) in ultra scaled CMOS.
Front – End Architecture
Figure 3.1 shows the IC block diagram.
Figure 3.1 Block diagram of the Sub-Harmonic I & Q receiver
57
example in automotive radars. In this scenario, we propose a
front-end
in 65nm CMOS.
that adequate performances are achieved in a
), low power solution (first below 100mW, to
Harmonic I & Q receiver
Chapter 3
58
A single-ended two stage low noise amplifier (LNA) is
followed by a current driven sub-harmonic passive mixer loaded
by a common gate base-band amplifier. The mixer
transconductor converts the signal into differential. Half
frequency LO provides 4 reference signals, phase shifted by 45°,
for down-conversion. Dividers for frequency synthesis are also
integrated.
Sub-harmonic mixing did not make in-roads in RF
products mainly because the LO synthesis is more complicate
and not counterbalanced by major advantages in performances.
But, at Ka band and mm-wave frequencies, the design of
passives is still critical, both in terms of accurate modeling and
quality. For this reason, for example, VCOs consume a significant
portion of the overall power and usually display a very limited
tuning range.
3.3 Frequency synthesis
In this work, 4 LO phases, spaced by 45°, are generated by
a ring of 4 LC tank VCOs, shown in figure 3.2.
Chapter 3
Figure 3.
They operate
variable capacitors.
oscillators coupling is muc
counterpart [
implemented and characterized separately. Measurements show
Figure 3.2 Multi-phase Voltage Controlled Oscillator
They operate at half frequency, with better quality of
variable capacitors. Moreover the penalty in phase noise due to
oscillators coupling is much less than in the quadrature oscillator
counterpart [3.3]. A standalone version of the LO generator is
implemented and characterized separately. Measurements show
59
at half frequency, with better quality of
Moreover the penalty in phase noise due to
h less than in the quadrature oscillator
A standalone version of the LO generator is
implemented and characterized separately. Measurements show
Chapter 3
60
26% frequency tuning range and a phase noise of -110dBc/Hz at
1MHz from 12.5 GHz. Each VCO in the ring consumes 3.7mW.
The phase noise penalty with respect to a single oscillator
drawing the same power is only 2dB. Maximum phase error is
<3°. In terms of phase noise figure of merit, the proposed 4
phase LO generator outperforms published coupled quadrature
oscillators and is comparable with single differential oscillators at
Ka Band. Tuning range is remarkably higher.
3.4 LNA design
To minimize the noise impact of the base-band amplifier,
featuring a 1GHz wide-bandwidth, and mixer, the LNA is
designed with a relatively large gain of 25 dB, mandating the use
of two stages, drawn in figure 3.3.
Chapter 3
Figure devices and ground
Gray components are parasitics. The input network is a
modified version of the inductively degenerated stage, adopted
for the following reasons: 1. the inductance value of L
by the conventional topology, is relatively high. In integrated
fashion, its self resonance is well below the operating frequency.
2. Capacitor C absorbs pad and spiral parasitic capacitance,
otherwise determining an unmatched reactive input com
The Π
choice of a different inductor value. Lowering
self-resonance though at the expense of an increased noise
contribution. In this design it is set to 400pH as the best
comprom
LC networks are device parasitic only. Ptap contacts to the
Figure 3.3 Low Noise Amplifier. Gray components represent devices and ground-plane parasitics.
Gray components are parasitics. The input network is a
modified version of the inductively degenerated stage, adopted
for the following reasons: 1. the inductance value of LG, required
by the conventional topology, is relatively high. In integrated
fashion, its self resonance is well below the operating frequency.
2. Capacitor C absorbs pad and spiral parasitic capacitance,
otherwise determining an unmatched reactive input component.
Π match introduces one degree of freedom allowing the
choice of a different inductor value. Lowering LG increases its
resonance though at the expense of an increased noise
contribution. In this design it is set to 400pH as the best
compromise. For maximum peak gain, capacitors in the output
LC networks are device parasitic only. Ptap contacts to the
61
Low Noise Amplifier. Gray components represent
Gray components are parasitics. The input network is a
modified version of the inductively degenerated stage, adopted
, required
by the conventional topology, is relatively high. In integrated
fashion, its self resonance is well below the operating frequency.
2. Capacitor C absorbs pad and spiral parasitic capacitance,
ponent.
match introduces one degree of freedom allowing the
increases its
resonance though at the expense of an increased noise
contribution. In this design it is set to 400pH as the best
ise. For maximum peak gain, capacitors in the output
LC networks are device parasitic only. Ptap contacts to the
Chapter 3
62
substrate are carefully placed, surrounding active devices, for
maximum capacitor quality factor (Q). Capacitors Cshunt, AC
coupling supply and ground, are particularly critical. Their
contacts to ground are placed as close as possible to devices
substrate contacts to make interconnects impedance negligible.
Moreover, not to degrade resonators Q, a low plate resistance
requires large capacitance, several pF in our design, mandating a
careful layout for a self-resonance beyond 30GHz.
Because of the single–ended topology of the amplifiers,
return paths are also extremely critical. Ground planes show a
negligible resistance but their reactance can severely impair
performances. Extensive electromagnetic simulations have been
performed to take this effect under control. The most critical
ground connections require a reactance below 3Ω, i.e. 20 pH
when totally inductive. To accommodate large signals, a variable
gain feature is provided in the second stage.
3.5 Mixer and Baseband Design
Figure 3.4 shows a simplified schematic of the
transconductor, mixer and base-band amplifier.
Chapter 3
Figure 3.transimpedance ampli
The sub
switches, mainly for voltage room reasons. A low impedance
load is preferred over the high impedance alternative to achieve
higher conversion
For better LO phase matching and minimum capacitive loading,
the switches are laid
frequency translation, the RF signal is converted into differential
making return signal paths less critical. The same single
differential converter/transconductor is shared between I&Q
Figure 3.4 I & Q Sub-Harmonic mixers and base-transimpedance amplifiers
The sub-harmonic mixer, current driven, employs passive
switches, mainly for voltage room reasons. A low impedance
load is preferred over the high impedance alternative to achieve
higher conversion gain and less sensitivity to device parasitics.
better LO phase matching and minimum capacitive loading,
the switches are laid-out as close as possible to the VCO. Prior to
frequency translation, the RF signal is converted into differential
making return signal paths less critical. The same single-ended to
differential converter/transconductor is shared between I&Q
63
-band
harmonic mixer, current driven, employs passive
switches, mainly for voltage room reasons. A low impedance
load is preferred over the high impedance alternative to achieve
and less sensitivity to device parasitics.
better LO phase matching and minimum capacitive loading,
out as close as possible to the VCO. Prior to
frequency translation, the RF signal is converted into differential
ed to
differential converter/transconductor is shared between I&Q
Chapter 3
64
signal paths and feeds the mixers with a 350µm length
differential transmission line with source and load impedance
matched. The base band trans-impedance amplifiers are single
stage with common gate input devices.
3.6 Layout and Experiments
The receiver has been fabricated in the 65nm RF CMOS
process from STMicroelectronics. Figure 3.5 shows the chip
micrograph.
Figure 3.5 Die microphotograph
Chapter 3
65
The die area, including bond pads, is 2.1 mm2, with the
core cell occupying 1.4 mm2. Total power dissipation is 92mW,
of which 40.8mW are consumed by the RF front-end, 28.8mW by
the base band amplifiers and 22.8mW by the LO generation
circuits (VCO and dividers).
Figure 3.6 shows the measured gain curves and noise
figure.
Figure 3.6 Measured Conversion-Gain and Noise Figure
Chapter 3
66
The gain can be varied by 8dB. The -3dB output
bandwidth at IF is 1GHz. The IIP3, measured injecting two
interferers, equally spaced in frequency, ~ 1GHz apart from the
peak gain, is -17dBm presently limited by the base-band
amplifier. The IIP2, measured at 50MHz output frequency,
injecting a double side-band interferer ~ 1GHz from peak gain is
0dBm. The LO tone coupled at the input signal port is -65dBm at
12GHz, and below -90 dBm at 24GHz, proving the attractiveness
of this topology for radar applications. I and Q mismatch is < 3°.
Table 3.I summarizes measured results.
Chapter 3
67
Table 3.I
Chapter 3
68
References
[3.1] S. Emami, C. Doan, A. Niknejad, R. Brodersen: “A Highly
Integrated 60GHz CMOS Front-End Receiver”, IEEE Intern.
Solid-State Circuits Conf. Dig. Tech Papers, pp.190-191,
Feb. 2007.
[3.2] B. Haydari, M. Bohsali, E. Adabi, A.M. Nicknejad : “Low
power mm-Wave Components up to 104GHz in 90nm
CMOS”, IEEE Intern. Solid-State Circuits Conf. Dig. Tech
Papers, pp.200-201, Feb. 2007.
[3.3] L. Romanò, S. Levantino, C. Samori, A. Lacaita:
“Multiphase LC Oscillators”, IEEE Transactions on
Circuits and Systems I, Vol.53, no.7, pp-1579-1588. July
2006.
Appendix A
69
Appendix A
A 750mV Fully Integrated
Direct Conversion Receiver Front-
End for GSM in 90nm CMOS
The design of RF integrated circuits, at the low voltage
allowed by sub-scaled technologies, is particularly challenging in
cellular phone applications where the received signal is
surrounded by huge interferers, determining an extremely high
dynamic range requirement. In-depth investigations of 1/f noise
sources and second order intermodulation distortion mechanisms
in direct down-conversion mixers have been carried out in the
recent past.
Appendix A
70
This chapter proposes a fully integrated receiver front-
end, including LNA and quadrature mixer, supplied at 750mV,
able to meet GSM specifications. In particular, the direct
downconverter employs a feedback loop to minimize second
order common mode intermodulation distortion, generated by a
pseudo-differential transconductor, adopted for minimum
voltage drop. For maximum dynamic range, the commutating
pair is set with an LC filter.
Prototypes, realized in a 90nm RFCMOS process, show the
following performances: 51dBm IIP2, minimum over 25 samples,
1dB desensitization point due to 3MHz blocker at -18dBm, 3.5dB
noise figure (NF), integrated between 1kHz-100kHz, 15kHz 1/f
noise corner.
The front-end IIP2 has also been characterized with the
mixer feedback loop switched off, resulting in an average
reduction of 18dB.
A.1 Introduction
In the last decade, the target of a highly integrated CMOS
solution has driven the development of wireless devices, now
including the radio frequency (RF) transceiver, the digital base-
band and the medium access control (MAC) layer. Signal
Appendix A
71
processing architectures, such as direct conversion to zero
intermediate frequency, more amenable to integration than
super-heterodyne, have been deeply investigated. Today, direct
conversion systems-on-chip (SoC’s) in CMOS technology are
available for diffused wireless standards like Bluetooth [A.1] and
WLAN’s [A.2].
Meanwhile, the effort toward fully integrated direct
conversion receivers for demanding applications, such as cell-
phones, has continued intensively [A.3, A.4]. Recently a GSM
CMOS SoC, integrated in a 130nm node, has been announced
[A.5]. Despite remarkable achieved results, none of the proposed
solutions lends itself to future scaled technologies, due to the
ever lower supply voltage available. While scaling is extremely
beneficial for digital circuits, it poses several challenges to the
analog section. In particular, the supply voltage, 1V in the 90nm
node, likely to be 750mV in 45nm [A.6], calls for new design
techniques to guarantee the required dynamic range, extremely
demanding especially in cellular wireless networks.
Due to the channel narrow-bandwidth, 1/f noise power is
of primary concern in GSM, especially in a CMOS
implementation. Typical 1/f noise frequency corners around 30
kHz are required [A.4, A.7]. Moreover, amplitude modulated
interferers determine a peculiar impairment in direct conversion
architectures, because any circuit block with quadratic non-
Appendix A
72
linearity acts as a rectifier. In a GSM system, when the handset is
tuned to a base-station, a burst coming from any other nearby
base-station can reach the receiver. The envelope of this burst is
demodulated around DC due to second order intermodulation
distortion. The AM suppression test [A.8] specifies a -31dBm
TDMA GMSK modulated interferer may be received, determining
an extremely high second order input intercept point (IIP2) of
46dBm not to degrade signal quality.
In particular at very low supply voltage operation, the
down-conversion mixer limits the achievable front-end dynamic
range because the low noise amplifier is narrow-band, filtering
out low frequency noise and intermodulation distortion
products. The work presented here shows that proper design
techniques allow RF front-end circuits meeting the tough
specification of GSM, even operating at a supply voltage as low
as 750mV [A.9]. In particular, the down-conversion mixer
employs a pseudo-differential input transconductor to save
voltage room. A feedback network to minimize common mode
second order intermodulation products, generated by the
transconductor, is introduced. The switching pair is set with an
LC filter to maximize IIP2 [A.10].
This chapter is organized as follows: paragraph 2 reviews
downconverter second order intermodulation mechanisms and
Appendix A
73
introduces a circuit technique achieving high IIP2 at low voltage.
Paragraph 3 details front-end circuits implementation, paragraph
4 presents experiments and paragraph 5 draws the conclusions.
A.2 Low voltage highly linear direct downconverters
Devices non-linearity and mismatches limit the achievable
IIP2 in CMOS direct downconverters. An in-depth analysis of the
under-lying physical mechanisms coupled with new circuit
techniques has lead to a solution able to meet the challenging
requirements of UMTS [A.10]. In particular, the generation of
intermodulation products in the switching pair of a Gilbert cell
has been addressed and an LC filter resonating out the parasitic
capacitance, loading the pair, introduced. The input
transconductor, shown in figure A.1a, achieves high linearity by
means of RC degeneration. High impedance at low frequency
maximizes IIP2, while low impedance at RF leads to high IIP3.
On the other hand, this downconverter, supplied at 1.8V,
does not lend itself to very low-voltage operation due to three
stacked devices in the core. While the supply voltage scales in
new technology nodes, the output voltage dynamics, set by large
interferers, cannot be reduced. Furthermore, devices need to be
biased in saturation. In particular, a high current source output
resistance is key to minimize second order intermodulation
Appendix A
74
distortion, i.e. the current source requires biasing with safety
margin from linear region. In fact, second order input intercept
voltage point (IIV2) is given by [A.10]:
( )
2
dsmm
g
rg14gIIV2
+⋅= (A.1)
with gm and g2 the transconductance and second order
conductance of each input device, respectively, and rds the
current source output resistance. Correspondingly, IIP2 is the
power dissipated in a 50Ω resistance.
The fully differential topology, shown in figure A.1b, a
suitable alternative when second order intermodulation
distortion is concerned, suffers from the same problem.
Furthermore, it proves a worse IIP3 performance [A.10].
The pseudo-differential transconductor, drawn in figure
A.1c, is very attractive, only requiring the drain voltage Vd being
higher than the device overdrive voltage Vov, lending to very low
voltage operation. Another merit is the very high achievable IIP3.
On the other hand, its major limit, deleterious in the frame-work
of direct conversion applications, is the poor IIP2 [A.11].
Appendix A
75
Appendix A
76
Figure A.1 Mixer transconductors topologies: a) RC degenerated, b) fully differential, c) pseudo-differential.
While differential second order intermodulation
distortion (IM2) components in the transconductor output
current can be easily eliminated through the LC filter adopted in
the switching stage [A.10], the common mode ones cannot, and
are partially converted into differential, at mixer output, due to
device mismatches.
In the following, we will investigate and quantify the
effect of IM2 components generated by the transconductor, and
propose a circuit technique achieving high linearity at extremely
low voltage supply.
Appendix A
77
A.2.1 Effects of transconductor IM2 on downconverter IIP2
Figure A.2 shows a double balanced Gilbert cell adopting
the LC filter to reduce switching pairs intermodulation distortion
[A.10]. The input transconductor is represented by a block.
Low-frequency, second order distortion components in
the transconductor output current spectrum, IIM2,1 and IIM2,2, can
be written as follows:
2
ΔIII IM2
CMIM2,IM2,1 += (A.2a)
2
ΔIII IM2
CMIM2,IM2,2 −= (A.2b)
where IIM2,CM and ∆IIM2 are the common mode and differential
components, respectively.
Appendix A
78
Figure A.2 Down-conversion mixer set with LC filter.
∆IIM2 is re-circulated by the differential inductor, thus not
contributing to mixer output. On the contrary, IIM2,CM contributes
to the overall differential downconverter IIP2 due to two distinct
Appendix A
79
mechanisms, determining common mode to differential
conversion.
First, IIM2,CM modulate the switching pairs biasing currents
and are transmitted at mixer output still as common mode
currents. Here, a mismatch ∆R between the load resistors
determines common mode to differential conversion. Because
∆R is a random variable, the resulting differential second order
intermodulation (IM2) output voltage is also a random variable,
with standard deviation IIM2,CM∙σ∆R, where σ∆R is ∆R standard
deviation.
The second mechanism is due to mismatch between
switching devices. Referring to figure A.2, the two pairs produce
low-frequency differential leakage gains L1 and L2, i.e. a
differential IM2 component appears in the mixer output current.
Also the leakage gains are random variables. If σL=σL1=σL2 is the
leakage gain standard deviation, the corresponding standard
deviation in the differential IM2 output voltage is given by
IIM2,CM∙√2σL∙R.
Because the two mechanisms are uncorrelated, the
expression for the differential IM2 voltage standard deviation at
mixer output (σVIM2,DIFF,OUT) is given by:
Appendix A
80
( ) ( )2
CMIM2,
2
CMIM2,OUTDIFF,IM2, σΔRIRσL2IσV ⋅+⋅⋅= (A.3)
The downconverter IIP2 (IIP2D) can be derived given the
transconductor common mode IIP2 (IIP2t,CM), and the signal
current gain (2/π):
( )2
2
CMt,D
R
σΔRσL2
1
π
2IIP2IIP2
+
⋅⋅=
(A.4)
From equation (4.4), the second order linearity
requirement for the transconductor can be determined.
Considering GSM receiver IIP2 specification is 46dBm, assuming
an LNA gain around 20dB, the downconverter minimum IIP2
requirement is 66dBm. IIP2 depends on mismatch between
nominally identical devices, i.e. a parameter with large variation
among different samples, and at least 10dB implementation
margin should be taken into account, to guarantee production
yield. Furthermore, considering the switching pair, set with LC
filter, determines an intrinsic IIP2 contribution roughly equal to
80dBm [A.10], the transconductor IIP2 should be in the 85-
Appendix A
81
90dBm range. Assuming typical mismatch between devices, the
common mode to differential conversion gain is about -50dB.
From equation (A.4), it follows IIP2t,CM should be around 45-
50dBm.
The RC degenerated solution is the only achieving such a
high IIP2 performance, provided the current source is safely
biased in saturation. To gain insight, figure A.3 plots IIP2 versus
device width W for the three alternatives, with 4mA biasing
current. In the RC degenerated solution, the current source
output resistance is 5kΩ, and Vds = 500mV. On the other hand,
from equation (A.1), IIP2 reduces with reducing output
resistance, i.e. when the voltage room is decreased, making this
alternative unsuitable.
Appendix A
82
Figure A.3 Intrinsic IIP2 of alternative transconductors: a) RC degenerated, b) fully differential, c) pseudo-differential.
A.2.2 Direct downconverter with input-output common mode
feedback
Preventing injection of common mode intermodulation
components into the switching stage represents the most
effective way to minimize input transconductor contribution to
overall downconverter IIP2. Observing the largest portion of
common mode intermodulation current is transmitted un-
altered at mixer output suggests keeping the output common
mode voltage under control by means of a feedback loop built
0
5
10
15
20
25
30
35
40
45
50
30 40 50 60 70 80 90 100
W[µµµµm]
IIP2[
dB
m] (b)
(a)
(c)
Appendix A
83
around the downconverter, as shown in figure A.4. An
operational amplifier senses the difference between the
common mode output voltage and a reference (VREF) and drives
a PMOS device (PCM) supplying the common mode current to the
input transconductor.
Appendix A
84
Figure A.4 Proposed mixer with common mode feedback loop.
Appendix A
85
The higher the common mode feedback (CMFB) loop gain
(Gloop) the lower the difference between output and reference
voltages and the lower the common mode intermodulation
current injected into the switching pair. Assuming, for the sake
of simplicity, the transconductor common mode current is
entirely due to a second order component (IIM2,CM) :
LOOP
LPLds,CMIM2,
LOOP
LOOPREFOUTCM,
G1
//RrI
G1
GVV
+⋅−
+⋅= (A.5)
( ) ( )
LOOP
2
CMIM2,
2
CMIM2,
LOOP
OLOUT,IM2,
CLOUT,DIFF,IM2,G1
σΔRIRσL2I
G1
σVσV
+
⋅+⋅⋅=
+= (A.6)
( )LPLds,Pm,LOOP //RrgA2
1G
CM⋅⋅= (A.7)
where VCM, out is the output common mode voltage, rds,PL
the output resistance of PL, σVIM2,OUT,CL and σVIM2,OUT,OL are the
variance of the output second order intermodulation distortion
voltage closed and open loop, respectively, A is the operational
amplifier gain, gm,PCM is the transconductance of PCM.
The loop is required to work at low-frequency, with a
bandwidth equal to the down-converted signal bandwidth, i.e.
DC to 100kHz in GSM. A large loop gain at this low-frequency can
be achieved without significant consumption penalty.
Appendix A
86
With a CMFB loop gain in excess of 40dB, even the
pseudo differential transconductor meets GSM requirements
with adequate margin, and is proposed in this design to achieve
minimum voltage drop and maximum IIP3.
Despite the differential nature of the mixer, the feedback
network is realized by means of a single common mode path, to
avoid possible unbalances due to differential device mismatches.
Furthermore, in this way it introduces only common mode noise.
On the contrary, the sensing resistors RCM are differential and,
due to mismatches, may convert part of the differential IM2 into
a common mode term, thus creating a fictitious error signal for
the CMFB loop. Nonetheless, this is a second order effect, with
negligible impact, originating from a differential IM2 at
downconverter output and mismatches between RCM resistors.
A.3 750mV Front-End
The proposed GSM direct conversion front-end block
diagram, comprising LNA and quadrature downconverters, is
shown in figure A.5. The prototype is designed to operate at a
minimum supply voltage of 750mV, and is tailored to the PCS
version of GSM, i.e. to the highest frequency allocation, with the
receive band spanning 1930MHz-1990MHz.
Appendix A
87
Figure A.5 Front end block diagram .
In the low-noise amplifier, inductive degeneration allows
minimizing NF while achieving impedance matching to the
source [A.12]. With reference to figure A.6, the gate inductors LG
are off-chip high quality factor devices, for NF minimization.
From simulations, with 5mA biasing current the minimum NF
occurs when the input pair devices M1-M2 aspect ratio is
400µm/0.1µm.
Appendix A
88
Figure A.6 Inductively degenerated low noise amplifier.
The source inductors Ls are realized by a single spiral with
central tap grounded, sized 4nH to synthesize a 100Ω differential
input resistance. With about 250fF pad capacitance, the 4.7nH
gate inductors tune the impedance matching to the PCS band.
Cascode devices M3-M4 have the same aspect ratio as the
input pair and they can be optimally interdigitated, minimizing
the input capacitance at the common node. A tuned LC load
provides selective gain in the PCS receive band. Inductors LL are
implemented as a single differential spiral with central tap tied
Appendix A
89
to the supply. A differential voltage-controlled resistor, realized
by the pMOS PG, allows reducing the LNA gain in presence of
strong signals. In order to further reduce the downconverter
noise contribution, the LNA gain is relatively high (23dB). From
simulations, NF=1.6dB and IIP3=0dBm.
To get rid of 1/f noise and low-frequency second order
distortion products, the LNA is AC coupled to the downconverter
shown in figure A.4. In the downconverter transconductor, non-
minimum channel length devices were adopted to reduce Vds
modulation due to the second harmonic of the local oscillator
(LO). With a device size of 125µm/0.2µm, and 5mA biasing
current, gm is 24mS, i.e. relatively high to reduce the effect of
low-frequency noise contribution of 400µm/0.3µm commutating
devices to front-end NF. In the switching stage, the 10nH
differential inductor LSW resonates out the parasitic capacitors at
the source nodes. The central tap is tied to the large 20pF CFAT
capacitor used to decouple the pairs at RF, thus enhancing IIP2
[A.10]. To achieve the maximum matching of the 250Ω load
resistors, polysilicon devices should be preferred over pMOS
current sources, featuring poorly matched output conductances.
On the other hand, the latter require minimum voltage room,
while the voltage drop across the resistors is not compatible with
750mV supply. With 10dB gain target for the downconverter,
and 2mA per branch, the 250Ω load resistors would require
Appendix A
90
500mV. The solution here adopted employs polysilicon resistors
shunting large 2000µm/2.5µm current sources PL. The output
common mode voltage is set to 500mV by the CMFB loop, i.e.
the resistors and the current sources provide 1mA each. From
simulations, the PL output resistance is >5kΩ. With 4mA flowing
in the downconverter load, the remaining 1mA is provided to the
transconductor by PCM. The differential output capacitance is
520pF and sets the output pole at 600kHz. In the CMFB loop, the
operational amplifier consumes only 100µA, and the overall
CMFB loop gain is 40dB.
As a final remark, the adopted transconductor allows the
downconverter to achieve excellent IIP3 and noise
performances. In fact, with moderate biasing currents, and
adopting the LC filter in the switching stage, the downconverter
IIP3 is limited by the transconductor. Choosing a pseudo
differential topology leads to superior IIP3 with respect to both
the fully differential and RC degenerated structures shown in
figure A.1a and A.1b.
From simulations, the downconverter achieves 10dB gain,
80dBm typical IIP2, limited by the switching stage, and 12dBm
IIP3. 1/f noise corner is about 180kHz, and the input-referred
rms noise voltage density is 5nV/√Hz.
Appendix A
91
A.4 Layout and Experiments
The front-end has been fabricated in a 90nm CMOS
process by STMicroelectronics. Figure A.7 shows the chip
photomicrograph. Die area is 4.3mm2, comprising LNA,
quadrature downconverters, biasing circuitry and ESD protected
pads. Active area is 2.7mm2. To minimize noise coupling from the
substrate, the LNA and downconverter RF devices are isolated in
p-wells connected to a dedicated ground. Active and passive
downconverter devices have been laid out as highly
interdigitated multiple fingers to minimize mismatches between
device pairs. In the switching stage, the RF and LO metal lines
cross orthogonally for minimum coupling, i.e. to minimize self-
mixing. The die is housed in a standard LQFP32 plastic package,
mounted on a low loss dielectric laminate (Rogers RO4003C, εr =
3.38, tanδ = 0.0021) for characterization.
Appendix A
92
Figure A.7 Chip photomicrograph
Figure A.8 shows the simulated and measured RF gain and
input reflection coefficient, S11. The RF gain is detected in-band,
at 10kHz, with the externally provided LO power of 4dBm. The -
3dB output bandwidth is 650kHz. A good agreement is found
between measurements and simulations, with 1dB difference in
the peak gain.
LNA
Appendix A
93
Figure A.8 Measured gain and S11
Figure A.9 shows the input-referred noise power spectral
density. The 1/f noise corner is as low as 15kHz, due to the high
front gain and the employed LC filter [A.10]. The corresponding
front-end noise figure, averaging noise between 1kHz and
100kHz, is 3.5dB.
1.7 1.8 1.9 2 2.1 2.218
20
22
24
26
28
30
32
34
-40
-30
-20
-10
0
Appendix A
94
Figure A.9 Input referred noise power spectral density
Second order intermodulation distortion is evaluated
injecting two tones 10kHz apart, at 6MHz from the received
signal to emulate the AM interferer specified by the standard.
Front-end IIP2 is expected to be limited by mismatch between
the downconverter commutating devices. Variations among 25
measured samples have been reported in figure A.10.
0 20 40 60 80 100-174
-172
-170
-168
-166
-164
-162
-160
Appendix A
95
Figure A.10 Front-end IIP2 for several different samples.
The minimum front-end IIP2 is 51dBm, corresponding to a
downconverter IIP2 of about 73dBm. A maximum of 68dBm is
found, with the average at 57dBm. In order to evaluate the
effectiveness of the proposed solution, the front-end IIP2 has
been characterized also with the downconverter CMFB loop
switched off. In this case, the downconverter IIP2 is expected to
be dominated by the pseudo differential transconductor. From
the analysis of paragraph 2, the downconverter IIP2 variance
should reduce to about 55dBm, i.e. the front-end IIP2 variance
should be in the order of 30dBm. Figure A.11 reports measured
45
50
55
60
65
70
75
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Sample #
IIP2
[dB
m]
Appendix A
96
data. The front-end minimum IIP2 is 35dBm, confirming the
beneficial effect of the CMFB loop.
Figure A.11 Front-end IIP2 when the feedback loop is switched off.
The front end output DC offset should be minimized in
order to prevent saturating the following stages of the receiver.
Figure A.12 shows the measured variation among 25 samples,
with a maximum value of 1.2mV, demonstrating the excellent
symmetry achieved in the layout.
30
35
40
45
50
55
60
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Sample #
IIP2
[d
Bm
]
Appendix A
97
Figure A.12 Front-end output offset voltage for several different samples.
The GSM standard specifies a -23dBm continuous wave
interferer 3MHz away from the received signal. Though not
source of intermodulation distortion, the blocker can determine
mixer gain de-sensitization especially in a low voltage solution.
Figure A.13 shows the front-end gain versus the blocker power,
indicating a 1dB drop at -21dBm. Taking into account about 3dB
insertion loss due to a commercial RF filter, the front end 1dB
de-sensitization point would be achieved at -18dBm blocker
input power, with 5dB margin on the standard specification.
-1.5
-1
-0.5
0
0.5
1
1.5
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Sample #
Ou
tpu
t D
C O
ffse
t [m
V]
Appendix A
98
Figure A.13 Front-end gain versus the power of a 3MHz interferer. 1dB de-sensitization point is -18dBm.
Third order intermodulation distortion is tested injecting
two tones, 800kHz and 1600kHz apart from the desired RF signal.
Measured IIP3 is -10.5dBm.
Although designed to work at 750mV, the front-end
proves to be functional down to 550mV. At this supply voltage
level the feedback amplifier starts compressing and the
resistance of mixer output devices reduces. From
measurements, the peak gain is 26dB, 1dB desensitization power
is –22dBm (-19dBm referred at RF filter input), average NF is
28
29
30
31
32
33
-40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20
3MHz blocker power [dBm]
Fro
nt-
En
d g
ain
[d
B]
Appendix A
99
3.5dB while 22 out of 25 samples still meet IIP2 requirement,
demonstrating the front – end potential for even lower supply
voltage operation.
Table A.I shows the measurement summary. The current
consumption is 15mA, 5mA for the LNA and 5mA each
downconverter.
Table A.I
6Gain Reduction [dB]
151/f Noise Corner [kHz]
51Minimum IIP2 [dBm]
3.5Noise Figure [dB]
4.3Die area [mm2]
-10.5IIP3 [dBm]
STMicroelectronics CMOS090Technology
LQFP 32Package
2.7Active area [mm2]
15Current consumption [mA]
0.75Voltage Supply [V]
31.5Voltage Gain [dB]
6Gain Reduction [dB]
151/f Noise Corner [kHz]
51Minimum IIP2 [dBm]
3.5Noise Figure [dB]
4.3Die area [mm2]
-10.5IIP3 [dBm]
STMicroelectronics CMOS090Technology
LQFP 32Package
2.7Active area [mm2]
15Current consumption [mA]
0.75Voltage Supply [V]
31.5Voltage Gain [dB]
Appendix A
100
A.5 Conclusions
CMOS technologies are scaling at such a fast pace that
the design of fully integrated RF circuits at the ever lower supply
voltage requires detailed investigation of the ultimate
mechanisms limiting linearity and noise in conventional circuit
topologies. In this chapter, we have proven the feasibility of a
fully integrated direct conversion front-end supplied at 750mV,
and easily portable down to 500mV, for a demanding application
such as GSM.
Appendix A
101
References
[A.1] J.Cheah, E.Kwek, E.Low, C.Quek, C.Yong, R.Enright,
J.Hirbawi, A.Lee, H.Xie, L.Wei, L.Luong, J.Pan, S.Yang,
W.Lau, W.Ngai, “Design of a Low-Cost Integrated 0.25µm
CMOS Bluetooth SOC in 16.5mm2 Silicon Area”, IEEE
International Solid-State Circuits Conference (ISSCC) Digest
of Technical Papers, February 2002
[A.2] S.Khorram, H.Darabi, Z.Zhou, Q.Li, B.Marholev, J.Chiu,
J.Castaneda, H.Chien, S.B.Anad, S.Wu, M.Pan,
R.Roofougaran, H.J.Kim, P.Lettieri, B.Ibrahim, J.J.Rael,
L.H.Tran, E.Geronaga, H.Yeh, T.Frost, J.Trachewsky, and
A.Rofougaran, “A Fully Integrated SOC for 802.11b in 0.18-
µm CMOS”, IEEE Journal of Solid-State Circuits, vol. 40, pp.
2492-2501, December 2005
[A.3] E.Song, Y.Koo, Y.J.Jung, D.H.Lee, S.Chu, S.I.Chae, “A
0.25µm CMOS Quad-Band GSM RF Transceiver Using an
Efficient LO Frequency Plan”, IEEE Journal of Solid-State
Circuits, vol. 40, pp. 1094-1106, May 2005
Appendix A
102
[A.4] P.Sivonen, J.Tervaluoto, N.Mikkola, and A.Parssinen, “A
1.2-V RF Front-End With On-Chip VCO for PCS 1900 Direct
Conversion Receiver in 0.13-µm CMOS”, IEEE Journal of
Solid-State Circuits, vol. 41, pp. 384-394, February 2006
[A.5] P.-H. Bonnaud, M. Hammes, A. Hanke, J. Kissing, R. Koch,
E. Labarre, C. Schwoerer, “A Fully Integrated SoC for
GSM/GPRS in 0.13µm CMOS”, IEEE International Solid-
State Circuits Conference (ISSCC) Digest of Technical
Papers, pp. 482-483, February 2006
[A.6] M.Iwai, A.Oishi, T.Sanuki, Y.Takegawa, T.Komoda,
Y.Morimasa, K.Ishimaru, M.Takayanagi, K.Eguchi,
D.Matsushita, K.Muraoka, K.Sunouchi, and T.Noguchi,
“45nm CMOS Platform Technology (CMOS6) with High
Density Embedded Memories”, Symposium on VLSI
Technology Digest of Technical Papers, June 2004
[A.7] H.Darabi and J.Chiu, “A Noise Cancellation Technique in
Active RF-CMOS Mixers”, IEEE Journal of Solid-State
Circuits, vol. 40, pp. 2628 - 2632, December 2005
Appendix A
103
[A.8] Digital Cellular Telecommunications System (Phase 2);
Radio Transmission and Reception, GSM Standard 05 05,
1999
[A.9] M.Brandolini, M.Sosio, F.Svelto, “A 750 mV 15 kHz 1/f
Noise Corner 51 dBm IIP2 Direct-Conversion Front-End for
GSM in 90nm CMOS”, IEEE International Solid-State
Circuits Conference (ISSCC) Digest of Technical Papers, pp.
470-471, February 2006
[A.10] M.Brandolini, P.Rossi, D.Sanzogni, F.Svelto, “A +78dBm
IIP2 CMOS Direct Downconversion Mixer for Fully
Integrated UMTS Receivers”, IEEE Journal of Solid State
Circuits, vol. 41, pp. 552 - 559, March 2006
[A.11] D.Manstretta, M.Brandolini, and F.Svelto, “Second –
Order Intermodulation Mechanisms in CMOS
Downconverters.”, IEEE Journal of Solid State Circuits, vol.
38, pp. 394-406, March 2003
[A.12] D.K.Shaeffer and T.H.Lee, “A 1.5-V, 1.5 GHz CMOS Low
Noise Amplifier”, IEEE Journal of Solid-State Circuits, vol.
32, pp. 745 – 759, May 1997
Appendix A
104
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105
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[1.1] C. Shannon “A Mathematical Theory of Communication”,
The Bell System Technical Journal, vol. 27, July – October
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[1.2] Title 47 of the Code of Federal Regulations (47 CFR), Part
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[1.3] L. Yujiri, M. Shoucri, P. Moffa, “Passive mm – Wave
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Chapter 2
[2.1] J. Lee, “A 3 to 8GHz Fast Hopping Frequency Synthesizer in
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[2.3] S.Dal Toso, A.Bevilacqua, M.Tiebout, S.Marsili, C.Sandner,
A.Gerosa, A.Neviani, “UWB Fast Hopping Frequency
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Technical Papers, pp. 124-125, Feb. 2008.
[2.4] J.R.Bergervoet, K.S.Harish, S.Lee, D.Leenaerts, R. van de
Beek, G. van der Weide, R.Roovers, “A WiMedia-
Compliant UWB Transceiver in 65nm CMOS” IEEE
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Chapter 3
[3.1] S. Emami, C. Doan, A. Niknejad, R. Brodersen: “A Highly
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Appendix A
[A.1] J.Cheah, E.Kwek, E.Low, C.Quek, C.Yong, R.Enright,
J.Hirbawi, A.Lee, H.Xie, L.Wei, L.Luong, J.Pan, S.Yang,
W.Lau, W.Ngai, “Design of a Low-Cost Integrated 0.25µm
CMOS Bluetooth SOC in 16.5mm2 Silicon Area”, IEEE
International Solid-State Circuits Conference (ISSCC) Digest
of Technical Papers, February 2002
[A.2] S.Khorram, H.Darabi, Z.Zhou, Q.Li, B.Marholev, J.Chiu,
J.Castaneda, H.Chien, S.B.Anad, S.Wu, M.Pan,
R.Roofougaran, H.J.Kim, P.Lettieri, B.Ibrahim, J.J.Rael,
L.H.Tran, E.Geronaga, H.Yeh, T.Frost, J.Trachewsky, and
A.Rofougaran, “A Fully Integrated SOC for 802.11b in 0.18-
µm CMOS”, IEEE Journal of Solid-State Circuits, vol. 40, pp.
2492-2501, December 2005
Bibliography
108
[A.3] E.Song, Y.Koo, Y.J.Jung, D.H.Lee, S.Chu, S.I.Chae, “A
0.25µm CMOS Quad-Band GSM RF Transceiver Using an
Efficient LO Frequency Plan”, IEEE Journal of Solid-State
Circuits, vol. 40, pp. 1094-1106, May 2005
[A.4] P.Sivonen, J.Tervaluoto, N.Mikkola, and A.Parssinen, “A
1.2-V RF Front-End With On-Chip VCO for PCS 1900 Direct
Conversion Receiver in 0.13-µm CMOS”, IEEE Journal of
Solid-State Circuits, vol. 41, pp. 384-394, February 2006
[A.5] P.-H. Bonnaud, M. Hammes, A. Hanke, J. Kissing, R. Koch,
E. Labarre, C. Schwoerer, “A Fully Integrated SoC for
GSM/GPRS in 0.13µm CMOS”, IEEE International Solid-
State Circuits Conference (ISSCC) Digest of Technical
Papers, pp. 482-483, February 2006
[A.6] M.Iwai, A.Oishi, T.Sanuki, Y.Takegawa, T.Komoda,
Y.Morimasa, K.Ishimaru, M.Takayanagi, K.Eguchi,
D.Matsushita, K.Muraoka, K.Sunouchi, and T.Noguchi,
“45nm CMOS Platform Technology (CMOS6) with High
Density Embedded Memories”, Symposium on VLSI
Technology Digest of Technical Papers, June 2004
Bibliography
109
[A.7] H.Darabi and J.Chiu, “A Noise Cancellation Technique in
Active RF-CMOS Mixers”, IEEE Journal of Solid-State
Circuits, vol. 40, pp. 2628 - 2632, December 2005
[A.8] Digital Cellular Telecommunications System (Phase 2);
Radio Transmission and Reception, GSM Standard 05 05,
1999
[A.9] M.Brandolini, M.Sosio, F.Svelto, “A 750 mV 15 kHz 1/f
Noise Corner 51 dBm IIP2 Direct-Conversion Front-End for
GSM in 90nm CMOS”, IEEE International Solid-State
Circuits Conference (ISSCC) Digest of Technical Papers, pp.
470-471, February 2006
[A.10] M.Brandolini, P.Rossi, D.Sanzogni, F.Svelto, “A +78dBm
IIP2 CMOS Direct Downconversion Mixer for Fully
Integrated UMTS Receivers”, IEEE Journal of Solid State
Circuits, vol. 41, pp. 552 - 559, March 2006
[A.11] D.Manstretta, M.Brandolini, and F.Svelto, “Second –
Order Intermodulation Mechanisms in CMOS
Downconverters.”, IEEE Journal of Solid State Circuits, vol.
38, pp. 394-406, March 2003
Bibliography
110
[A.12] D.K.Shaeffer and T.H.Lee, “A 1.5-V, 1.5 GHz CMOS Low
Noise Amplifier”, IEEE Journal of Solid-State Circuits, vol.
32, pp. 745 – 759, May 1997
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