Villalobos Aquino Antonio Avance 5 Marco Teorico

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PROFESOR(A): MC. SUSANA MONICA ROMAN NJERA

UNIDAD: 2 UNIDAD

ALUMNO: VILLALOBOS AQUINO ANTONIOCRUZ SNCHEZ ENRIQUE AVELINO

SOSA DOMNGUEZ JOS SEBASTINTOLEDO SARBIA CECAR

TRABAJO: MARCO TEORICO

GRUPO: VI-C

ING. ELECTRNICA

13-MAR-2013


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Marco terico histrico

Automatizacin llenado de tanques

Tarea a realizar, control independiente del llenado de 2 tanques de agua con una sola

bomba. Contamos con:

-2 switches de nivel (flotadores) N1 y N2 con contactos NO y NC (*)

-2 vlvulas actuadas elctricamente por solenoide S1 y S2

Adicionales

-2 rels con contactos NO K1 y K2

- 1 contactor K3

Funcionamiento:

Al bajar el nivel en cualquiera de los tanques, se cierra el contacto NO del flotador,alimentando la solenoide y la bobina del rel correspondiente (Kn). Con esto abre lavlvula y cierra el contacto NO del rel, alimentando el contactor K3 que alimenta labomba. Las salidas de los rels K1 y K2 estn conectadas en paralelo, por lo queconforman una compuerta lgica , es decir, activarn a K3 en el caso de quecualquiera de los dos rels (o ambos) est activo.

(*) Solo es necesario el contacto NO, o sea aquel que est abierto cuando el tanque

est lleno, aunque comnmente este tipo de switches tiene ambos contactos.

Variantes:1)El sistema permite algunas variantes, por ejemplo, la posibilidad deprescindir de los rels K1 y K2 utilizando un presostato en la bomba. Cuando ambassolenoides estn cerradas, la presin a la salida de la bomba sube, apagndose cuandosupera el umbral seteado. Al abrir una o ambas solenoides, la presin cae y elpresostato cierra, encendiendo la bomba.


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2) Si la etapa de control est alimentada con tensin continua , tambin se puedeprescindir de los rels K1 y K2, sustituyndolos por 2 diodos D1 y D2. La funcin de losrels en el circuito original es aislar las seales de salida de los flotadores. Si no los

usramos, estaramos uniendo elctricamente ambas solenoides que abriran juntas alactivarse cualquiera de los flotadores. Si la etapa de control es de continua, los diodosbloquean la alimentacin de cada solenoide a travs del flotador opuesto.

Vemos como al cerrar por ejemplo N1, la corriente se establece a travs de la bobina deK3, pero es bloqueada por D2, de manera que no se alimenta S2. El circuito de potenciase dibuja aparte porque trabaja con otra tensin, en este caso 230 o 400 VAC.

Existen otras variantes al circuito, por ejemplo, el uso de sensores de nivel porelectrodos, que requieren alimentacin para funcionar y actan sobre un rel que tienenincorporado. El siguiente ejemplo utiliza dos de estos sensores, y adems con uncomportamiento diferente: el tanque 1 tiene prioridad de llenado sobre el tanque 2, deforma que la activacin del sensor de nivel N1 inhibe el funcionamiento de N2.


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Por ltimo un sistema un poco ms complejo, volvemos a los flotadores, llenaremossolo un tanque por vez, pero ahora la prioridad la tendr el primer tanque que se vace,inhibiendo el llenado del otro hasta que se complete su nivel.

El presostato es redundante y se utiliza como medida de seguridad ante la falla de unade las solenoides.

E1 temporizador t1, retrasa unos milisegundos (500 en este caso) la entrada delcontactor K1, para evitar situaciones de inestabilidad al energizar el sistema con ambostanques vacos (quienes hayan visto vibrar un rel saben de que estoy hablando). Estohace que el tanque 2 sea quien comience el llenado al energizar el sistema con tanques

vacos.

Los contactos NC de los rels K1 y K2 se utilizan para inhibir el llenado del tanqueopuesto y los NO encienden la bomba, al estar energizada una de las vlvulas

solenoides.


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AUTOMATIZACION DEL CONTROL DE NIVEL DE UN TANQUE DEAGUA

Karol Paola Yanes Snchez

Universidad Pontificia Bolivariana,

Va a Piedecuesta km 7,

[email protected]

[email protected]

Bucaramanga

1. INTRODUCCIN

El desarrollo de la produccin industrial est ligado a la electrnica a travs desus aplicaciones de medicin, monitoreo y automatizacin de los procesos, permitiendotener productos de alta calidad y bajo costo.

La tecnologa de medicin industrial es un elemento clave para garantizar lacalidad constante de los productos, la optimizacin de los procesos y la seguridad yproteccin del entorno.

El desarrollo cada da ms acelerado de la electrnica nos ha estado brindandonuevos sistemas de Medicin de Nivel, cada vez ms sofisticados a costos menores. Noobstante, muchos principios fsicos tradicionales tienen particularidades tcnicas oprcticas que los mantienen siempre vigentes.

En la actualidad existen una gran variedad de mecanismos y dispositivosutilizados como sensores de nivel anlogos o digitales. Entre los que se destacan: detubo de vidrio, indicador magntico, capacitivos, inductivos y de flotador.

Con este proyecto se implement un sistema de control de nivel basado en unsensor de flotador anlogo, que permite conocer el nivel en tiempo real.

El sistema desarrollado permite al operario definir el nivel deseado en el tanquemediante una interfaz, que acciona diferentes mecanismos externos como bombas yelectrovlvulas para la entrada y salida de lquido del tanque, hasta alcanzar los nivelesdeseados con muy alta precisin.


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La figura 3 muestra el diagrama de bloques del sistema implementado, el cual consta delas siguientes partes:

Sensor Teclado

LCD: Display de cristal liquido Electrovlvula Bomba de agua Microcontrolador Circuito de control

Este sensor de nivel es anlogo, el cual se realizo con un potencimetro lineal de 10k,

conectado como eje a una polea. La cuerda en un extremo sostiene un sensor Tanque

principal electrovlvula Tanque auxiliar Bomba Microcontrolador Teclado Display decristal lquido (LCD)

Electrovlvula Bomba de agua Circuito de control Circuito de control Sensor flotadordentro del tanque principal que mide el nivel y en el otro extremo un contrapeso; estemecanismo a medida que sube o baja el nivel hace rodar la polea que contiene elpotencimetro como eje que a su vez hace girar el potencimetro el cual enva unaseal de voltaje anlogo al ADC del microcontrolador que la convierte en digital y realizatodo el control del sistema.

3.2. Teclado

Se pueden ingresar valores de 5 en 5 desde 0 hasta 100, para nmeros inferiores a100 se ingresa precedido de un cero (015). Despus se ingresa la tecla numeral (#)para enviar el numero al microcontrolador y este proceda hacer el control del nivel deltanque, como una especie de enter, cuando se desea borrar el numero ingresado sepuede realizar oprimiendo la tecla (*). Si el numero que se le ingreso al teclado no esmltiplo de 5, o no va incluido en la escala de nivel del tanque; no se visualizara en elLCD y el microcontrolador no realiza ninguna accin hasta que el numero ingresado nosea el correcto; es decir no se encuentre entre el rango definido y no sea mltiplo de 5.

Este teclado se maneja por el microcontrolador 16F877A, donde el nmero ingresadoes visualizado en el LCD, y comparado por medio del microcontrolador con el nivelactual de tanque a controlar.


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3.3. Display de cristal lquido (LCD)

Esta interfaz permite visualizar inicialmente la presentacin del proyecto, seguido deesto el nivel actual del tanque principal, y el nivel deseado por el operador (set point).

3.4. electrovlvulaLa electrovlvula posee un sistema on/off, es decir mientras no le llegue una sealalterna de voltaje se mantendr cerrada y cuando le llega una seal de voltaje se abre ydeja pasar el fluido de agua. Esta electrovlvula es alimentada por 120V por lo tantorequiere de un circuito de potencia para ser acoplado al microcontrolador.

3.5. Bomba de agua

Esta bomba de agua es electro-sumergible y se encuentra ubicada en el tanqueauxiliar, donde tiene un control de la salida del fluido manual, es decir un mximo y un

mnimo, donde mientras le llegue una seal alterna esta se encuentra en el mximo ycuando no le llega ninguna seal de voltaje esta se cierra totalmente. Esta bomba esalimentada a 120V y requiere de un circuito de potencia para ser acoplada almicrocontrolador igualmente que como se realiz con la electrovlvula.

3.6. microcontrolador

Se utilizo un microcontrolador P16f877 de microchip el cual tiene cuatro puertos, ya quese requera controlar un teclado, un LCD, una bomba, una electrovlvula y un sensoranlogo. Donde tiene como entradas la seal de voltaje anloga proveniente del

potencimetro lineal la cual permiti utilizar la funcin ADC del microcontrolador, y elteclado donde se ingresa un set point que es comparado con el nivel actual que es dadopor el sensor anlogo. Como salidas tiene el LCD donde se visualiza el valor ingresadoen el teclado y las seales de control que van al circuito de potencia para activar laelectrovlvula y la bomba de agua.

3.7. Circuito de potencia

Este circuito de potencia se implement tanto para la activacin de la electrovlvulacomo para la activacin de la bomba de agua, ya que estos elementos se alimenta convoltaje alterno y requieren de un circuito que aisl el circuito de control con el de

potencia. El circuito de potencia se realiz con un optoacoplador (moc3031) al cual lellega la seal proveniente del microcontrolador y este a su vez es conectado con untriac (BTA06), que va a la electrovlvula o bamba y a la seal alterna de la red.

4. PROYECCION

El siguiente paso en el desarrollo de este proyecto es la conformacin de un sistema decontrol de inventario que permita hacer todo desde una computadora, con alarmas,estadsticas, grficos de actividad, "logueo" automtico de eventos, facturacin porvolumen o por masa, y mucho ms, con la mxima exactitud alcanzable hoy.


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Material:

1- SN74LS04N 1- SN74LS27N

9- 1RK 3- 1N4004

2- RAS-0510 2- BC547-B

2- TRTG-02 12- Electrodos

1- E100-50R 1-MC7805CT


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Marco terico conceptual

El control automtico de procesos

Los procesos industriales no son procesos en estado estable, sino que son dinmicos

por naturaleza, los cambios ocurren constantemente y si no se realizan las accionescorrectivas apropiadas, las variables importantes del proceso, especialmente aquellasrelacionadas con la seguridad, pueden desviarse de los valores de diseo. El controlautomtico pretende mantener las variables de proceso, temperatura, presin, flujos,composiciones y dems en un valor de operacin ptimo (Smith & Corripio, 1997). Elcontrol automtico desempea una funcin vital en el avance de la ingeniera y laciencia, y es parte importante e integral de los procesos modernos industriales y demanufactura. En la actualidad los lazos de control son un elemento esencial para lamanufactura econmica y prspera de casi cualquier producto, con un enfoque hacia lacalidad y constancia en la produccin, mejorar el rendimiento y la seguridad, reduccin

del desperdicio y de energa consumida, adems de reducir el trabajo rutinario yaburrido de los operadores (Healey, 1967; Ogata, 1998).

Sistemas de control

Un sistema o proceso est formado por un conjunto de elementos relacionados entre s,que producen seales de salida en funcin de seales de entrada. Las variables queafectan un proceso se clasifican en entradas, que denota el efecto de los alrededoressobre el proceso, y salidas, que denota el efecto del proceso sobre los alrededores.

Las entradas pueden clasificarse en variables manipuladas, si sus valores puedenajustarse libremente por el ser humano o un sistema automtico, y variables dedisturbio, si sus valores no se controlan del todo. Las salidas se pueden clasificar a su

vez en variables medibles, si sus valores se conocen por medicin directa, y variablesno medibles, cuyo valor no se puede medir en forma directa (Molina, 1998).


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Control retroalimentado

En un sistema de control retroalimentado la variable controlada se mide por un sensor,se transmite hacia el controlador, y se compara con el valor de referencia o punto deconsigna, la diferencia entre ambas variables, conocida como el error, se utiliza para

modificar la variable manipulada, tendiendo a reducir la diferencia, y este proceso serepite continuamente.

Control adelantado

Los sistemas en los cuales la salida del proceso no afecta la accin de control sedenominan sistemas de control en lazo abierto. En otras palabras, en un sistema decontrol en lazo abierto no se mide la salida ni se retroalimenta para compararla con unareferencia, por lo que el controlador trabaja independientemente de la salida delproceso.


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Tipos de medicin de nivel


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Medicin directa

Varilla o sonda: Consiste en una varilla o regla graduada, de la longitud convenientepara introducirla dentro del depsito. La determinacin del nivel se efecta por la lecturadirecta de la longitud mojada por el lquido. En el momento de la lectura el tanque debe

estar abierto a presin atmosfrica. Se emplea en tanques de agua a presinatmosfrica. Cinta y plomada: este sistema consta de una cinta graduada y un plomo enla punta. Se emplea cuando es difcil que la varilla tenga acceso al fondo del tanque.Tambin se usa midiendo la distancia desde la superficie del lquido hasta la partesuperior del tanque, obteniendo el nivel por diferencia. Visor de vidrio: consiste en untubo de vidrio con su extremo inferior conectado al tanque generalmente mediante tresvlvulas (dos de cierre de seguridad en los extremos del tubo, para impedir el escapedel lquido en caso de rotura del cristal y una de purga).Funciona por principio de vasoscomunicantes. El nivel de vidrio va acompaado de una regla graduada. Se empleapara presiones hasta 7 bar. A presiones ms elevadas el vidrio es grueso, de seccinrectangular y est protegido por una armadura metlica.


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Medicin por presin hidrosttica

Manomtrico: consiste en un manmetro conectado directamente a la parte inferior deltanque. El manmetro mide la presin debida a la altura de lquido que existe entre elnivel del tanque y el eje del instrumento. Slo sirve para fluidos limpios, ya que los

lquidos sucios pueden hacer perder la elasticidad del fuelle. La medicin est limitada atanques abiertos y el nivel viene influido por las variaciones de densidad del lquido.Membrana: Usa una membrana conectada al instrumento receptor por un tubo estanco.El peso de la columna de lquido sobre el rea de la membrana comprime el aire internoa una presin igual a la ejercida por la columna de lquido. El instrumento es delicado yaque una fuga del aire contenido en el diafragma destruira la calibracin del instrumento.

Medicin por presin diferencial

El medidor de presin diferencial consiste en un diafragma en contacto con el lquido deltanque, que permite medir la presin hidrosttica en un punto del fondo del tanque. Enun tanque abierto esta presin es proporcional a la altura del lquido en ese punto y a supeso especfico. El diafragma forma parte de un transmisor neumtico o electrnico depresin diferencial.


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MPIC16F84A

Data Sheet

18-pin Enhanced FLASH/EEPROM

8-bit Microcontroller


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Note the following details of the code protection feature on PICmicroMCUs.

The PICmicro family meets the specifications contained in the Microchip Data Sheet.

Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.The person doing so may be engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any othersemiconductor manufacturercan guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.If you have any further questions about this matter, please contact the local sales office nearest to you.

Information contained in this publication regarding deviceapplications and the like is intended through suggestion onlyand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.No representation or warranty is given and no liability isassumed by Microchip Technology Incorporated with respectto the accuracy or use of such information, or infringement ofpatents or other intellectual property rights arising from suchuse or otherwise. Use of Microchips products as critical com-ponents in life support systems is not authorized except withexpress written approval by Microchip. No licenses are con-veyed, implicitly or otherwise, under any intellectual propertyrights.

Trademarks

The Microchip name and logo, the Microchip logo, PIC, PICmicro,PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL,MPLAB and The Embedded Control Solutions Company are reg-istered trademarks of Microchip Technology Incorporated in theU.S.A. and other countries.

Total Endurance, ICSP, In-Circuit Serial Programming, Filter-Lab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM,MPLINK, MPLIB, PICC, PICDEM, PICDEM.net, ICEPIC,Migratable Memory, FanSense, ECONOMONITOR, SelectMode and microPort are trademarks of Microchip TechnologyIncorporated in the U.S.A.

Serialized Quick Term Programming (SQTP) is a service markof Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of theirrespective companies.

2001, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.

Printed on recycled

paper.

Microchip received QS-9000 quality systemcertification for its worldwide headquarters,design and wafer fabrication facilities inChandlerand Tempe, Arizona in July 1999. TheCompanys quality system processes andprocedures are QS-9000 compliant for itsPICmicro 8-bit MCUs, KEELOQ code hoppingdevices, Serial EEPROMs and microperipheralproducts. In addition, Microchips qualitysystem for the design and manufacture ofdevelopment systems is ISO 9001 certified.


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PIC1

6F

84A

PIC1

6F

84A

M PIC16F84A18-pin EnhancedFLASH/EEPROM 8-Bit Microcontroller

High Performance RISC CPU Features:

Only 35 single word instructions to learn

All instructions single-cycle except for programbranches which are two-cycle

Operating speed: DC - 20 MHz clock inputDC - 200 ns instruction cycle

1024 words of program memory

68 bytes of Data RAM

64 bytes of Data EEPROM

14-bit wide instruction words

8-bit wide data bytes

15 Special Function Hardware registers Eight-level deep hardware stack

Direct, indirect and relative addressing modes

Four interrupt sources:

- External RB0/INT pin

- TMR0 timer overflow

- PORTB interrupt-on-change

- Data EEPROM write complete

Peripheral Features:

High current sink/source for direct LED drive

Pin Diagrams

PDIP, SOIC

RA2 1

RA3 2

RA4/T0CKI 3

MCLR 4

VSS 5

RB0/INT 6

RB1 7

RB2 8

RB3 9

SSOP

RA2 1

RA3 2

RA4/T0CKI 3

MCLR 4

VSS 5

VSS 6

RB0/INT 7

RB1 8

RB2 9

18 RA1

17 RA0

16 OSC1/CLKIN

15 OSC2/CLKOUT

14 VDD

13 RB7

12 RB6

11 RB5

10 RB4

20 RA1

19 RA018 OSC1/CLKIN

17 OSC2/CLKOUT

16 VDD

15 VDD

14 RB7

13 RB6

12 RB5

- 25 mA sink max. per pin- 25 mA source max. per pin

TMR0: 8-bit timer/counter with 8-bitprogrammable prescaler

RB3 10 11 RB4

Special Microcontroller Features:

10,000 erase/write cycles Enhanced FLASHProgram memory typical

10,000,000 typical erase/write cycles EEPROMData memory typical

EEPROM Data Retention > 40 years

In-Circuit Serial Programming (ICSP) - via

two pins Power-on Reset (POR), Power-up Timer (PWRT),

Oscillator Start-up Timer (OST)

Watchdog Timer (WDT) with its own On-Chip RCOscillator for reliable operation

Code protection

Power saving SLEEP mode Selectable oscillator options

CMOS Enhanced FLASH/EEPROMTechnology:

Low power, high speed technology

Fully static design

Wide operating voltage range:

- Commercial: 2.0V to 5.5V

- Industrial: 2.0V to 5.5V Low power consumption:

- < 2 mA typical @ 5V, 4 MHz

- 15 A typical @ 2V, 32 kHz

- < 0.5 A typical standby current @ 2V


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Table of Contents1.0 Device Overview .......................................................................................................................................................................... 32.0 Memory Organization................................................................................................................................................................... 53.0 Data EEPROM Memory ............................................................................................................................................................. 134.0 I/O Ports ..................................................................................................................................................................................... 155.0 Timer0 Module ........................................................................................................................................................................... 196.0 Special Features of the CPU...................................................................................................................................................... 217.0 Instruction Set Summary ............................................................................................................................................................ 358.0 Development Support................................................................................................................................................................. 439.0 Electrical Characteristics............................................................................................................................................................ 4910.0 DC/AC Characteristic Graphs .................................................................................................................................................... 6111.0 Packaging Information................................................................................................................................................................ 71

Appendix A: Revision History .............................................................................................................................................................. 75Appendix B: ConversionConsiderations.............................................................................................................................................. 76Appendix C: Migration from Baseline to Mid-Range Devices .............................................................................................................. 78Index .................................................................................................................................................................................................... 79On-Line Support................................................................................................................................................................................... 83ReaderResponse ................................................................................................................................................................................ 84PIC16F84A Product Identification System........................................................................................................................................... 85

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of yourMicrochip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will berefined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.We welcome your feedback.

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Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist forcurrent devices. As device/documentation issues become known to us, we will publish an errata sheet . The errata will specify therevision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

1.0 DEVICE OVERVIEW

This document contains device specific information forthe operation of the PIC16F84A device. Additionalinformation may be found in the PICmicro Mid-Range Reference Manual, (DS33023), which may bedownloaded from the Microchip website. The Refer-

ence Manual should be considered a complementarydocument to this data sheet, and is highly recom-mended reading for a better understanding of thedevice architecture and operation of the peripheralmodules.

The PIC16F84A belongs to the mid-range family of thePICmicro microcontroller devices. A block diagram ofthe device is shown in Figure 1-1.

The program memory contains 1K words, which trans-lates to 1024 instructions, since each 14-bit programmemory word is the same width as each device instruc-tion. The data memory (RAM) contains 68 bytes. DataEEPROM is 64 bytes.

There are also 13 I/O pins that are user-configured ona pin-to-pin basis. Some pins are multiplexed with other

device functions. These functions include: External interrupt

Change on PORTB interrupt

Timer0 clock input

Table 1-1 details the pinout of the device with descrip-tions and details for each pin.

FIGURE 1-1: PIC16F84A BLOCK DIAGRAM

FLASHProgramMemory

13Program Counter

Data Bus 8

EEPROM Data Memory

EEPROM

1K x 14 8 Level Stack(13-bit)

RAMFile Registers

68 x 8

EEDATA Data Memory64 x 8

ProgramBus 14 7 RAM Addr EEADR

Instruction Register

5 Direct Addr

AddrMux

7 IndirectAddr

TMR0

FSR reg

STATUS reg

8

RA4/T0CKI

InstructionDecode &

Control

TimingGeneration

ALU

W reg

MUX

8I/O Ports

RA3:RA0

RB7:RB1

RB0/INT

OSC2/CLKOUTOSC1/CLKIN

MCLR VDD, VSS


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Legend: I= input O = Output I/O = Input/Output P = Power = Not used TTL = TTL input ST = Schmitt Trigger input

TABLE 1-1: PIC16F84A PINOUT DESCRIPTION

Pin NamePDIPNo.

SOICNo.

SSOPNo.

I/O/PType

BufferType

Description

OSC1/CLKIN 16 16 18 I ST/CMOS(3)Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 15 19 O Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode. In RC mode,OSC2 pin outputs CLKOUT, which has 1/4 thefrequency of OSC1 and denotes the instructioncycle rate.

MCLR 4 4 4 I/P ST Master Clear (Reset) input/programming voltageinput. This pin is an active low RESET to the device.

RA0

RA1

RA2

RA3

RA4/T0CKI

17

18

1

2

3

17

18

1

2

3

19

20

1

2

3

I/O

I/O

I/O

I/O

I/O

TTL

TTL

TTL

TTL

ST

PORTA is a bi-directional I/O port.

Can also be selected to be the clock input to the

TMR0 timer/counter. Output is open drain type.

RB0/INT

RB1

RB2

RB3

RB4

RB5

RB6

RB7

6

7

8

9

10

11

12

13

6

7

8

9

10

11

12

13

7

8

9

10

11

12

13

14

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

TTL/ST(1)

TTL

TTL

TTL

TTL

TTL

TTL/ST(2)

TTL/ST(2)

PORTB is a bi-directional I/O port. PORTB can besoftware programmed for internal weak pull-up onall inputs.

RB0/INT can also be selected as an externalinterrupt pin.

Interrupt-on-change pin.



Serial programming clock.Interrupt-on-change pin.Serial programming data.

VSS 5 5 5,6 P Ground reference for logic and I/O pins.

VDD 14 14 15,16 P Positive supply for logic and I/O pins.

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.


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Indirect addr.(1) Indirect addr.(1)

TMR0 OPTION_REGPCL PCL

STATUS STATUS

FSR FSR

PORTA TRISA

PORTB TRISB

EEDATA EECON1EEADR EECON2(1)

PCLATH PCLATH

INTCON INTCON

68GeneralPurpose

Registers(SRAM)

Mapped(accesses)in Bank 0

2.2 Data Memory Organization

The data memory is partitioned into two areas. The first

FIGURE 2-2: REGISTER FILE MAP -PIC16F84A

is the Special Function Registers (SFR) area, while thesecond is the General Purpose Registers (GPR) area.The SFRs control the operation of the device.

Portions of data memory are banked. This is for both

the SFR area and the GPR area. The GPR area isbanked to allow greater than 116 bytes of generalpurpose RAM. The banked areas of the SFR are for theregisters that control the peripheral functions. Bankingrequires the use of control bits for bank selection.These control bits are located in the STATUS Register.Figure 2-2 shows the data memory map organization.

Instructions MOVWF and MOVF can move values fromthe W register to any location in the register file (F),and vice-versa.

The entire data memory can be accessed eitherdirectly using the absolute address of each register fileor indirectly through the File Select Register (FSR)

(Section 2.5). Indirect addressing uses the presentvalue of the RP0 bit for access into the banked areas ofdata memory.

Data memory is partitioned into two banks whichcontain the general purpose registers and the specialfunction registers. Bank 0 is selected by clearing theRP0 bit (STATUS). Setting the RP0 bit selects Bank1. Each Bank extends up to 7Fh (128 bytes). The firsttwelve locations of each Bank are reserved for theSpecial Function Registers. The remainder are Gen-eral Purpose Registers, implemented as static RAM.

2.2.1 GENERAL PURPOSE REGISTERFILE

Each General Purpose Register (GPR) is 8-bits wideand is accessed either directly or indirectly through theFSR (Section 2.5).

The GPR addresses in Bank 1 are mapped to

FileAddress

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

4Fh50h

7FhBank 0 Bank 1

FileAddress

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh8Ch

CFhD0h

FFh

addresses in Bank 0. As an example, addressing loca-tion 0Ch or 8Ch will access the same GPR.

Unimplemented data memory location, read as 0.

Note 1: Not a physical register.


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2.3 Special Function Registers

The Special Function Registers (Figure 2-2 andTable 2-1) are used by the CPU and Peripheralfunctions to control the device operation. Theseregisters are static RAM.

The special function registers can be classified into twosets, core and peripheral. Those associated with thecore functions are described in this section. Thoserelated to the operation of the peripheral features aredescribed in the section for that specific feature.

TABLE 2-1: SPECIAL FUNCTION REGISTER FILE SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPower-on

RESET

Detailson page

Bank 000h INDF Uses contents of FSR to address Data Memory (not a physical register) ---- ---- 1101h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 2002h PCL Low Order 8 bits of the Program Counter (PC) 0000 0000 1103h STATUS(2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 8

04h FSR Indirect Data Memory Address Pointer 0 xxxx xxxx 1105h PORTA(4) RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx 16

06h PORTB(5) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx 1807h Unimplemented location, read as '0' 08h EEDATA EEPROM Data Register xxxx xxxx 13,1409h EEADR EEPROM Address Register xxxx xxxx 13,140Ah PCLATH Write Buffer for upper 5 bits of the PC(1) ---0 0000 11

0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 10Bank 180h INDF Uses Contents of FSR to address Data Memory (not a physical register) ---- ---- 1181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 9

82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 1183h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 8

84h FSR Indirect data memory address pointer 0 xxxx xxxx 1185h TRISA PORTA Data Direction Register ---1 1111 1686h TRISB PORTB Data Direction Register 1111 1111 1887h Unimplemented location, read as '0' 88h EECON1 EEIF WRERR WREN WR RD ---0 x000 1389h EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 14

0Ah PCLATH Write buffer for upper 5 bits of the PC(1) ---0 0000 11

0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 10Legend: x= unknown, u= unchanged. -= unimplemented, read as '0', q= value depends on conditionNote 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC. The contents

of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC are never trans-ferred to PCLATH.

2: The TO and PD status bits in the STATUS register are not affected by a MCLR Reset.

3: Other (non power-up) RESETS include: external RESET through MCLR and the Watchdog Timer Reset.4: On any device RESET, these pins are configured as inputs.5: This is the value that will be in the port output latch.


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2.3.1 STATUS REGISTER

The STATUS register contains the arithmetic status ofthe ALU, the RESET status and the bank select bit fordata memory.

As with any register, the STATUS register can be thedestination for any instruction. If the STATUS register isthe destination for an instruction that affects the Z, DCor C bits, then the write to these three bits is disabled.These bits are set or cleared according to device logic.Furthermore, the TO and PD bits are not writable.Therefore, the result of an instruction with the STATUSregister as destination may be different than intended.

For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS registeras 000u u1uu (where u = unchanged).

Only the BCF, BSF, SWAPF and MOVWF instructionsshould be used to alter the STATUS register (Table 7-2),because these instructions do not affect any status bit.

Note 1: The IRP and RP1 bits (STATUS)are not used by the PIC16F84A andshould be programmed as cleared. Use ofthese bits as general purpose R/W bits isNOT recommended, since this may affectupward compatibility with future products.

2: The C and DC bits operate as a borrow

and digit borrow out bit, respectively, insubtraction. See the SUBLW and SUBWFinstructions for examples.

3: When the STATUS register is thedestination for an instruction that affectsthe Z, DC or C bits, then the write to thesethree bits is disabled. The specified bit(s)will be updated according to device logic

REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC Cbit 7 bit 0

bit 7-6 Unimplemented: Maintain as 0

bit 5 RP0: Register Bank Select bits (used for direct addressing)

01 = Bank 1 (80h - FFh)00 = Bank 0 (00h - 7Fh)

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, orSLEEP instruction0 = A WDT time-out occurred

bit 3 PD: Power-down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarityis reversed)1 = A carry-out from the 4th low order bit of the result occurred0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity isreversed)1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note: A subtraction is executed by adding the twos complement of the second operand.For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low orderbit of the source register.

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0- n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown


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2.3.2 OPTION REGISTER

The OPTION register is a readable and writableregister which contains various control bits to configurethe TMR0/WDT prescaler, the external INT interrupt,TMR0, and the weak pull-ups on PORTB.

REGISTER 2-2: OPTION REGISTER (ADDRESS 81h)

Note: When the prescaler is assigned tothe WDT (PSA = 1), TMR0 has a 1:1prescaler assignment.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Bit Value TMR0 Rate WDT Rate

000001010011100101110111

1 : 21 : 41 : 81 : 161 : 321 : 641 : 1281 : 256

1 : 11 : 21 : 41 : 81 : 161 : 321 : 641 : 128

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

- n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown


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2.3.3 INTCON REGISTER

The INTCON register is a readable and writableregister that contains the various enable bits for allinterrupt sources.

Note: Interrupt flag bits are set when an interruptcondition occurs, regardless of the state ofits corresponding enable bit or the globalenable bit, GIE (INTCON).

REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE EEIE T0IE INTE RBIE T0IF INTF RBIFbit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts0 = Disables all interrupts

bit 6 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE Write Complete interrupts0 = Disables the EE Write Complete interrupt

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit1 = Enables the TMR0 interrupt0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit1 = The RB0/INT external interrupt occurred (must be cleared in software)0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)0 = None of the RB7:RB4 pins have changed state




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movlw 0x20 ;initialize pointermovwf FSR ;to RAM

NEXT clrf INDF ;clear INDF registerincf FSR ;inc pointerbtfss FSR,4 ;all done?goto NEXT ;NO, clear next

2.4 PCL and PCLATH

The program counter (PC) specifies the address of theinstruction to fetch for execution. The PC is 13 bitswide. The low byte is called the PCL register. This reg-ister is readable and writable. The high byte is calledthe PCH register. This register contains the PC

bits and is not directly readable or writable. If the pro-gram counter (PC) is modified or a conditional test istrue, the instruction requires two cycles. The secondcycle is executed as a NOP. All updates to the PCH reg-ister go through the PCLATH register.

2.4.1 STACK

The stack allows a combination of up to 8 program callsand interrupts to occur. The stack contains the returnaddress from this branch in program execution.

Mid-range devices have an 8 level deep x 13-bit widehardware stack. The stack space is not part of eitherprogram or data space and the stack pointer is not

readable or writable. The PC is PUSHed onto the stackwhen a CALL instruction is executed or an interruptcauses a branch. The stack is POPed in the event of aRETURN, RETLW or a RETFIE instruction execution.PCLATH is not modified when the stack is PUSHed orPOPed.

After the stack has been PUSHed eight times, the ninthpush overwrites the value that was stored from the firstpush. The tenth push overwrites the second push (andso on).

2.5 Indirect Addressing; INDF andFSR Registers

The INDF register is not a physical register. AddressingINDF actually addresses the register whose address iscontained in the FSR register (FSR is a pointer). This isindirect addressing.

EXAMPLE 2-1: INDIRECT ADDRESSING

Register file 05 contains the value 10h

Register file 06 contains the value 0Ah

Load the value 05 into the FSR register

A read of the INDF register will return the valueof 10h

Increment the value of the FSR register by one(FSR = 06)

A read of the INDF register now will return thevalue of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce00h. Writing to the INDF register indirectly results in ano-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 20h-2Fhusing indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: HOW TO CLEAR RAMUSING INDIRECTADDRESSING

CONTINUE

: ;YES, continue

An effective 9-bit address is obtained by concatenatingthe 8-bit FSR register and the IRP bit (STATUS), asshown in Figure 2-3. However, IRP is not used in thePIC16F84A.


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Addressesmap back toBank 0

(3) (3)

FIGURE 2-3: DIRECT/INDIRECT ADDRESSING

Direct Addressing Indirect Addressing

RP1 RP0 6 From Opcode 0 IRP 7 (FSR) 0

(2) (2)

Bank Select Location SelectBank Select

Location Select

DataMemory(1)

00h

0Bh0Ch

4Fh50h

7Fh

00 01

80h

FFh

Bank 0 Bank 1

Note 1: For memory map detail, see Figure 2-2.

2: Maintain as clear for upward compatibility with future products.3: Not implemented.


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3.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writableduring normal operation (full VDD range). This memoryis not directly mapped in the register file space. Insteadit is indirectly addressed through the Special FunctionRegisters. There are four SFRs used to read and write

this memory. These registers are: EECON1

EECON2 (not a physically implemented register)

EEDATA

EEADR

EEDATA holds the 8-bit data for read/write, andEEADR holds the address of the EEPROM locationbeing accessed. PIC16F84A devices have 64 bytes ofdata EEPROM with an address range from 0h to 3Fh.

The EEPROM data memory allows byte read and write.A byte write automatically erases the location andwrites the new data (erase before write). The EEPROMdata memory is rated for high erase/write cycles. Thewrite time is controlled by an on-chip timer. The write-time will vary with voltage and temperature as well asfrom chip to chip. Please refer to AC specifications forexact limits.

When the device is code protected, the CPU maycontinue to read and write the data EEPROM memory.The device programmer can no longer accessthis memory.

Additional information on the Data EEPROM is avail-able in the PICmicro Mid-Range Reference Manual(DS33023).

REGISTER 3-1: EECON1 REGISTER (ADDRESS 88h)

U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEIF WRERR WREN WR RD

bit 7 bit 0

bit 7-5 Unimplemented: Read as '0'

bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)0 = The write operation is not complete or has not been started

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated(any MCLR Reset or any WDT Reset during normal operation)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles0 = Inhibits write to the EEPROM

bit 1 WR: Write Control bit

1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bitcan only be set (not cleared) in software.

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (notcleared) in software.

0 = Does not initiate an EEPROM read




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BCF STATUS, RP0 ; Bank 0MOVF EEDATA, W ; W = EEDATA

Require

d

Sequen

ce

3.1 Reading the EEPROM DataMemory

To read a data memory location, the user must write theaddress to the EEADR register and then set control bitRD (EECON1). The data is available, in the verynext cycle, in the EEDATA register; therefore, it can be

read in the next instruction. EEDATA will hold this valueuntil another read or until it is written to by the user(during a write operation).

EXAMPLE 3-1: DATA EEPROM READBCF STATUS, RP0 ; Bank 0

MOVLW CONFIG_ADDR ;

MOVWF EEADR ; Address to read

BSF STATUS, RP0 ; Bank 1BSF EECON1, RD ; EE Read

3.2 Writing to the EEPROM Data

MemoryTo write an EEPROM data location, the user must firstwrite the address to the EEADR register and the datato the EEDATA register. Then the user must follow aspecific sequence to initiate the write for each byte.

EXAMPLE 3-2: DATA EEPROM WRITEBSF STATUS, RP0 ; Bank 1

BCF INTCON, GIE ; Disable INTs.

BSF EECON1, WREN ; Enable Write

MOVLW 55h ;

Additionally, the WREN bit in EECON1 must be set toenable write. This mechanism prevents accidental writesto data EEPROM due to errant (unexpected) code exe-cution (i.e., lost programs). The user should keep theWREN bit clear at all times, except when updatingEEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit willbe inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit iscleared in hardware and the EE Write CompleteInterrupt Flag bit (EEIF) is set. The user can eitherenable this interrupt or poll this bit. EEIF must becleared by software.

3.3 Write Verify

Depending on the application, good programmingpractice may dictate that the value written to the DataEEPROM should be verified (Example 3-3) to thedesired value to be written. This should be used in

applications where an EEPROM bit will be stressednear the specification limit.

Generally, the EEPROM write failure will be a bit whichwas written as a 0, but reads back as a 1 (due toleakage off the bit).

EXAMPLE 3-3: WRITE VERIFYBCF STATUS,RP0 ; Bank 0

: ; Any code

: ; can go here

MOVF EEDATA,W ; Must be in Bank 0

BSF STATUS,RP0 ; Bank 1MOVWF EECON2 ; Write 55hMOVLW AAh ;

MOVWF EECON2 ; Write AAhBSF EECON1,WR ; Set WR bit

; begin write

BSF INTCON, GIE ; Enable INTs.

The write will not initiate if the above sequence is notexactly followed (write 55h to EECON2, write AAh toEECON2, then set WR bit) for each byte. We stronglyrecommend that interrupts be disabled during thiscode segment.

READ

BSF EECON1, RD ; YES, Read the

; value writtenBCF STATUS, RP0 ; Bank 0

;

; Is the value written

; (in W reg) and

; read (in EEDATA)

; the same?

;

SUBWFEEDATA, W ;

BTFSSSTATUS, Z ; Is difference 0?

GOTO WRITE_ERR ; NO, Write error

TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPower-onReset

Value onall otherRESETS

08h EEDATA EEPROM Data Register xxxx xxxx uuuu uuuu09h EEADR EEPROM Address Register xxxx xxxx uuuu uuuu88h EECON1 EEIF WRERR WREN WR RD ---0 x000 ---0 q00089h EECON2 EEPROM Control Register 2 ---- ---- ---- ----Legend: x= unknown, u= unchanged, -= unimplemented, read as '0', q= value depends upon condition.

Shaded cells are not used by data EEPROM.


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EN

4.0 I/O PORTS

Some pins for these I/O ports are multiplexed with analternate function for the peripheral features on the

FIGURE 4-1: BLOCK DIAGRAM OFPINS RA3:RA0

Datadevice. In general, when a peripheral is enabled, thatpin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the

PICmicro Mid-Range Reference Manual (DS33023).

4.1 PORTA and TRISA Registers

Bus

WRPort

D Q

CK Q

Data Latch

VDD

P

NPORTA is a 5-bit wide, bi-directional port. The corre-sponding data direction register is TRISA. Setting aTRISA bit (= 1) will make the corresponding PORTA pinan input (i.e., put the corresponding output driver in aHi-Impedance mode). Clearing a TRISA bit (= 0) will

D Q

WRTRIS

CK Q

VSS

make the corresponding PORTA pin an output (i.e., putthe contents of the output latch on the selected pin).

Note: On a Power-on Reset, these pins are con-figured as inputs and read as '0'.

Reading the PORTA register reads the status of the

TRIS Latch

RD TRIS

TTLInputBuffer

pins, whereas writing to it will write to the port latch. Allwrite operations are read-modify-write operations.Therefore, a write to a port implies that the port pins areread. This value is modified and then written to the portdata latch.

Pin RA4 is multiplexed with the Timer0 module clockinput to become the RA4/T0CKI pin. The RA4/T0CKIpin is a Schmitt Trigger input and an open drain output.

All other RA port pins have TTL input levels and fullCMOS output drivers.

EXAMPLE 4-1: INITIALIZING PORTABCF STATUS, RP0 ;

Q D

EN

RD Port

Note: I/O pins have protection diodes to VDD and VSS.

FIGURE 4-2: BLOCK DIAGRAM OF PINRA4

DataBus

CLRF PORTA ; Initialize PORTA by; clearing output

; data latches

BSF STATUS, RP0 ; Select Bank 1

WRPort

D Q

CK QN RA4 pin

MOVLW 0x0F ; Value used toData Latch

; initialize data

; direction

MOVWF TRISA ; Set RA as inputs

; RA4 as output

WRTRIS

D Q

CK Q

VSS

; TRISA are always

; read as 0.TRIS Latch

RD TRIS

SchmittTriggerInputBuffer

Q D

EN

RD Port

TMR0 Clock Input

Note: I/O pins have protection diodes to VDD and VSS.


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TABLE 4-1: PORTA FUNCTIONS

Name Bit0 Buffer Type Function

RA0 bit0 TTL Input/outputRA1 bit1 TTL Input/outputRA2 bit2 TTL Input/output

RA3 bit3 TTL Input/outputRA4/T0CKI bit4 ST Input/output or external clock input for TMR0.Output is open drain type.

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPower-on

Reset

Value on allother

RESETS

05h PORTA RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu85h TRISA TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are unimplemented, read as '0'.


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P

4.2 PORTB and TRISB Registers

PORTB is an 8-bit wide, bi-directional port. The corre-sponding data direction register is TRISB. Setting a

FIGURE 4-3: BLOCK DIAGRAM OFPINS RB7:RB4

VDD

TRISB bit (= 1) will make the corresponding PORTB pinan input (i.e., put the corresponding output driver in a

RBPU(1) WeakPull-up

Hi-Impedance mode). Clearing a TRISB bit (= 0) will Data BusData Latch

make the corresponding PORTB pin an output (i.e., putthe contents of the output latch on the selected pin).

D Q

WR PortCK

I/O pin(2)

EXAMPLE 4-2: INITIALIZING PORTB TRIS Latch

BCF

CLRFSTATUS, RP0 ;

PORTB ;

;Initialize PORTB by WR TRISclearing output

D

CK TTLInput; data latches Buffer

BSF STATUS, RP0 ; Select Bank 1MOVLW 0xCF ; Value used to

; initialize data a c ; direction Q D

MOVWF TRISB ; Set RB as inputs; RB as outputs Set RBIF RD Port EN; RB as inputs

Each of the PORTB pins has a weak internal pull-up. Asingle control bit can turn on all the pull-ups. This is per-formed by clearing bit RBPU (OPTION). The weakpull-up is automatically turned off when the port pin isconfigured as an output. The pull-ups are disabled on a

From otherRB7:RB4 pins

Q D

EN

RD Port

Power-on Reset.

Four of PORTBs pins, RB7:RB4, have an interrupt-on-change feature. Only pins configured as inputs cancause this interrupt to occur (i.e., any RB7:RB4 pinconfigured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB7:RB4)are compared with the old value latched on the lastread of PORTB. The mismatch outputs of RB7:RB4are ORed together to generate the RB Port Change

Note 1: TRISB = 1 enables weak pull-up(if RBPU = 0 in the OPTION_REG register).

2: I/O pins have diode protection to VDD and VSS.

FIGURE 4-4: BLOCK DIAGRAM OFPINS RB3:RB0

VDD

RBPU

(1)

WeakP Pull-upInterrupt with flag bit RBIF (INTCON).

Data BusData Latch

This interrupt can wake the device from SLEEP. Theuser, in the Interrupt Service Routine, can clear theinterrupt in the following manner:

D Q

WRPortCK

I/O pin(2)

TRIS Latcha) Any read or write of PORTB. This will end the

mismatch condition.D Q

TTLInput

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.Reading PORTB will end the mismatch condition andallow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operationswhere PORTB is only used for the interrupt-on-changefeature. Polling of PORTB is not recommended whileusing the interrupt-on-change feature.

WR TRIS

RB0/INT

CK

RD TRIS

RD Port

Buffer

Q D

EN

Schmitt TriggerBuffer

RD Port

Note 1: TRISB = 1 enables weak pull-up(if RBPU = 0 in the OPTION_REG register).

2: I/O pins have diode protection to VDD and VSS.


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TABLE 4-3: PORTB FUNCTIONS

Name Bit Buffer Type I/O Consistency Function

RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input.Internal software programmable weak pull-up.

RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.

RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.RB4 bit4 TTL Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.RB5 bit5 TTL Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.RB6 bit6 TTL/ST(2) Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up. Serial programming clock.RB7 bit7 TTL/ST(2) Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up. Serial programming data.Legend: TTL = TTL input, ST = Schmitt Trigger.Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPower-on

Reset

Value onall otherRESETS

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 111181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 11110Bh,8Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x0000 000uLegend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.


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ProgrammablePrescaler

5.0 TIMER0 MODULE

The Timer0 module timer/counter has the followingfeatures:

8-bit timer/counter

Readable and writable

Internal or external clock select

Edge select for external clock

8-bit software programmable prescaler

Interrupt-on-overflow from FFh to 00h

Figure 5-1 is a simplified block diagram of the Timer0module.

Additional information on timer modules is available inthe PICmicro Mid-Range Reference Manual(DS33023).

5.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.

Timer mode is selected by clearing bit T0CS(OPTION_REG). In Timer mode, the Timer0 mod-ule will increment every instruction cycle (without pres-caler). If the TMR0 register is written, the increment isinhibited for the following two instruction cycles. Theuser can work around this by writing an adjusted valueto the TMR0 register.

Counter mode is selected by setting bit T0CS(OPTION_REG). In Counter mode, Timer0 willincrement, either on every rising or falling edge of pinRA4/T0CKI. The incrementing edge is determined bythe Timer0 Source Edge Select bit, T0SE(OPTION_REG). Clearing bit T0SE selects the ris-ing edge. Restrictions on the external clock input are

discussed below.

When an external clock input is used for Timer0, it mustmeet certain requirements. The requirements ensurethe external clock can be synchronized with the internalphase clock (TOSC). Also, there is a delay in the actualincrementing of Timer0 after synchronization.

Additional information on external clock requirementsis available in the PICmicro Mid-Range Reference

Manual, (DS33023).

5.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0module, or as a postscaler for the Watchdog Timer,respectively (Figure 5-2). For simplicity, this counter isbeing referred to as prescaler throughout this datasheet. Note that there is only one prescaler availablewhich is mutually exclusively shared between the Timer0module and the Watchdog Timer. Thus, a prescalerassignment for the Timer0 module means that there is noprescaler for the Watchdog Timer, and vice-versa.

The prescaler is not readable or writable.

The PSA and PS2:PS0 bits (OPTION_REG)determine the prescaler assignment and prescale ratio.

Clearing bit PSA will assign the prescaler to the Timer0module. When the prescaler is assigned to the Timer0module, prescale values of 1:2, 1:4, ..., 1:256 areselectable.

Setting bit PSA will assign the prescaler to the WatchdogTimer (WDT). When the prescaler is assigned to theWDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable.

When assigned to the Timer0 module, all instructionswriting to the TMR0 register (e.g., CLRF 1, MOVWF 1,BSF 1,etc.) will clear the prescaler. When assigned toWDT, a CLRWDT instruction will clear the prescaleralong with the WDT.

Note: Writing to TMR0 when the prescaler isassigned to Timer0 will clear the prescalercount, but will not change the prescalerassignment.

FIGURE 5-1: TIMER0 BLOCK DIAGRAM

RA4/T0CKIpin

FOSC/4 0

1

T0SE

PSOUT1

0

3

Sync withInternal

Clocks

(2 Cycle Delay)

PSOUT

Data Bus

8

TMR0

Set Interrupt

T0CSPS2, PS1, PS0 PSA Flag bit T0IF

on Overflow

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG).2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).


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5.2.1 SWITCHING PRESCALERASSIGNMENT

The prescaler assignment is fully under software con-trol (i.e., it can be changed on the fly during programexecution).

Note: To avoid an unintended device RESET, a

specific instruction sequence (shown in thePICmicro Mid-Range Reference Man-ual, DS33023) must be executed whenchanging the prescaler assignment fromTimer0 to the WDT. This sequence mustbe followed even if the WDT is disabled.

5.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-ister overflows from FFh to 00h. This overflow sets bitT0IF (INTCON). The interrupt can be masked byclearing bit T0IE (INTCON). Bit T0IF must becleared in software by the Timer0 module Interrupt Ser-vice Routine before re-enabling this interrupt. TheTMR0 interrupt cannot awaken the processor fromSLEEP since the timer is shut-off during SLEEP.

FIGURE 5-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (= FOSC/4)Data Bus

0 M

RA4/T0CKIU

pin X1

1M

SYNC0

U 2X Cycles

8

TMR0 reg

T0SET0CS

PSA Set Flag bit T0IFon Overflow

0MU

Watchdog 1 XTimer

8-bit Prescaler

8

PSA

8 - to - 1 MUX PS2:PS0

WDT Enable bit0 1

M U X PSA

WDTTime-out

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG).

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on

POR,BOR

Value on allother

RESETS

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu0Bh,8Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 111185h TRISA PORTA Data Direction Register ---1 1111 ---1 1111Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.


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6.0 SPECIAL FEATURES OF THECPU

What sets a microcontroller apart from otherprocessors are special circuits to deal with the needs ofreal time applications. The PIC16F84A has a host ofsuch features intended to maximize system reliability,

minimize cost through elimination of externalcomponents, provide power saving operating modesand offer code protection. These features are:

OSC Selection

RESET

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

Interrupts

Watchdog Timer (WDT)

SLEEP

Code Protection

ID Locations In-Circuit Serial Programming (ICSP)

The PIC16F84A has a Watchdog Timer which can beshut-off only through configuration bits. It runs off itsown RC oscillator for added reliability. There are twotimers that offer necessary delays on power-up. One isthe Oscillator Start-up Timer (OST), intended to keep

the chip in RESET until the crystal oscillator is stable.The other is the Power-up Timer (PWRT), which pro-vides a fixed delay of 72 ms (nominal) on power-uponly. This design keeps the device in RESET while thepower supply stabilizes. With these two timers on-chip,most applications need no external RESET circuitry.

SLEEP mode offers a very low current power-down

mode. The user can wake-up from SLEEP throughexternal RESET, Watchdog Timer Time-out or throughan interrupt. Several oscillator options are provided toallow the part to fit the application. The RC oscillatoroption saves system cost while the LP crystal optionsaves power. A set of configuration bits are used toselect the various options.

Additional information on special features is availablein the PICmicro Mid-Range Reference Manual(DS33023).

6.1 Configuration Bits

The configuration bits can be programmed (read as '0'),

or left unprogrammed (read as '1'), to select variousdevice configurations. These bits are mapped inprogram memory location 2007h.

Address 2007h is beyond the user program memoryspace and it belongs to the special test/configurationmemory space (2000h - 3FFFh). This space can onlybe accessed during programming.

REGISTER 6-1: PIC16F84A CONFIGURATION WORD

R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u

CP CP CP CP CP CP CP CP CP CP PWRTE WDTE F0SC1 F0SC0

bit13 bit0

bit 13-4 CP: Code Protection bit1 = Code protection disabled0 = All program memory is code protected

bit 3 PWRTE: Power-up Timer Enable bit1 = Power-up Timer is disabled0 = Power-up Timer is enabled

bit 2 WDTE: Watchdog Timer Enable bit1 = WDT enabled0 = WDT disabled

bit 1-0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator10 = HS oscillator01 = XT oscillator00 = LP oscillator


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Ranges Tested:

Mode Freq OSC1/C1 OSC2/C2

XT 455 kHz2.0 MHz4.0 MHz

47 - 100 pF15 - 33 pF15 - 33 pF

47 - 100 pF15 - 33 pF15 - 33 pF

HS 8.0 MHz10.0 MHz

15 - 33 pF15 - 33 pF

15 - 33 pF15 - 33 pF

Note: Recommended values of C1 and C2 areidentical to the ranges tested in this table.Higher capacitance increases the stabilityof the oscillator, but also increases thestart-up time. These values are for designguidance only. Since each resonator hasits own characteristics, the user shouldconsult the resonator manufacturer for theappropriate values of external compo-nents.

R

6.2 Oscillator Configurations

6.2.1 OSCILLATOR TYPES

The PIC16F84A can be operated in four differentoscillator modes. The user can program two

FIGURE 6-2: EXTERNAL CLOCK INPUTOPERATION (HS, XT ORLP OSCCONFIGURATION)

configuration bits (FOSC1 and FOSC0) to select one ofClock from OSC1these four modes:

LP Low Power Crystal Ext. System PIC16FXX

XT Crystal/Resonator

HS High Speed Crystal/Resonator

RC Resistor/Capacitor

Open OSC2

6.2.2 CRYSTAL OSCILLATOR/CERAMICRESONATORS

In XT, LP, or HS modes, a crystal or ceramic resonatoris connected to the OSC1/CLKIN and OSC2/CLKOUTpins to establish oscillation (Figure 6-1).

FIGURE 6-1: CRYSTAL/CERAMIC

RESONATOR OPERATION(HS, XT OR LP OSCCONFIGURATION)

TABLE 6-1: CAPACITOR SELECTION FORCERAMIC RESONATORS

C1(1)

XTAL

OSC1

RF )

ToInternalLogic

C2(1)

(2)S

OSC2

(3

SLEEP

PIC16FXX

Note 1: See Table 6-1 for recommended valuesof C1 and C2.

2: A series resistor (RS) may be requiredfor AT strip cut crystals.

The PIC16F84A oscillator design requires the use of aparallel cut crystal. Use of a series cut crystal may givea frequency out of the crystal manufacturersspecifications. When in XT, LP, or HS modes, thedevice can have an external clock source to drive theOSC1/CLKIN pin (Figure 6-2).

Note: When using resonators with frequenciesabove 3.5 MHz, the use of HS mode ratherthan XT mode, is recommended. HS modemay be used at any VDD for which thecontroller is rated.


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Mode Freq OSC1/C1 OSC2/C2

LP 32 kHz200 kHz

68 - 100 pF15 - 33 pF

68 - 100 pF15 - 33 pF

XT 100 kHz2 MHz4 MHz

100 - 150 pF15 - 33 pF15 - 33 pF

100 - 150 pF15 - 33 pF15 - 33 pF

HS 4 MHz20 MHz

15 - 33 pF15 - 33 pF

15 - 33 pF15 - 33 pF

Note: Higher capacitance increases the stabilityof the oscillator, but also increases thestart-up time. These values are for designguidance only. Rs may be required in HSmode, as well as XT mode, to avoid over-driving crystals with low drive level specifi-cation. Since each crystal has its owncharacteristics, the user should consult thecrystal manufacturer for appropriate

values of external components.For VDD > 4.5V, C1 = C2 30 pF is recom-mended.

TABLE 6-2: CAPACITOR SELECTIONFOR CRYSTAL OSCILLATOR

6.2.3 RC OSCILLATOR

For timing insensitive applications, the RC deviceoption offers additional cost savings. The RC oscillatorfrequency is a function of the supply voltage, theresistor (REXT) values, capacitor (CEXT) values, andthe operating temperature. In addition to this, the oscil-lator frequency will vary from unit to unit due to normalprocess parameter variation. Furthermore, thedifference in lead frame capacitance between packagetypes also affects the oscillation frequency, especiallyfor low CEXT values. The user needs to take intoaccount variation, due to tolerance of the externalR and C components. Figure 6-3 shows how an R/Ccombination is connected to the PIC16F84A.

FIGURE 6-3: RC OSCILLATOR MODEVDD

REXT

CEXT

VSS

FOSC/4

OSC1

OSC2/CLKOUT

InternalClock

PIC16FXX

Recommended values: 5 k REXT 100 kCEXT > 20pF


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6.3 RESET

The PIC16F84A differentiates between various kindsof RESET:

Power-on Reset (POR) MCLR during normal operation MCLR during SLEEP

WDT Reset (during normal operation)

WDT Wake-up (during SLEEP)

Figure 6-4 shows a simplified block diagram of theOn-Chip RESET Circuit. The MCLR Reset path has anoise filter to ignore small pulses. The electrical speci-fications state the pulse width requirements for theMCLR pin.

Some registers are not affected in any RESET condition;their status is unknown on a POR and unchanged in anyother RESET. Most other registers are reset to a RESETstate on POR, MCLR or WDT Reset during normal oper-ation and on MCLR during SLEEP. They are not affectedby a WDT Reset during SLEEP, since this RESET isviewed as the resumption of normal operation.

Table 6-3 gives a description of RESET conditions forthe program counter (PC) and the STATUS register.Table 6-4 gives a full description of RESET states for allregisters.The TO and PD bits are set or cleared differently in dif-ferent RESET situations (Section 6.7). These bits areused in software to determine the nature of the RESET.

FIGURE 6-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

WDT WDT

SLEEP

VDD

Module

VDD RiseDetect

OST/PWRT

Time-outReset

Power-on Reset S

OSC1/CLKIN

On-ChipRC Osc(1)

OST

10-bit Ripple Counter

PWRT

10-bit Ripple Counter

Chip_ResetR Q

Enable PWRTSee Table 6-5

Enable OST

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.2: See Table 6-5.

TABLE 6-3: RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER

Condition Program Counter STATUS Register

Power-on Reset 000h 0001 1xxx

MCLR during normal operation 000h 000u uuuuMCLR during SLEEP 000h 0001 0uuu

WDT Reset (during normal operation) 000h 0000 1uuu

WDT Wake-up PC + 1 uuu0 0uuu

Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu

Legend: u = unchanged, x = unknownNote 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).


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6.4 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip whenVDD rise is detected (in the range of 1.2V - 1.7V). Totake advantage of the POR, just tie the MCLR pindirectly (or through a resistor) to VDD. This willeliminate external RC components usually needed to

create Power-on Reset. A minimum rise time for VDDmust be met for this to operate properly. See ElectricalSpecifications for details.

When the device starts normal operation (exits theRESET condition), device operating parameters (volt-age, frequency, temperature, etc.) must be met toensure operation. If these conditions are not met, thedevice must be held in RESET until the operating con-ditions are met.

For additional information, refer to Application NoteAN607, "Power-up Trouble Shooting."

The POR circuit does not produce an internal RESETwhen VDD declines.

6.6 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024oscillator cycle delay (from OSC1 input) after thePWRT delay ends (Figure 6-6, Figure 6-7, Figure 6-8and Figure 6-9). This ensures the crystal oscillator orresonator has started and stabilized.

The OST time-out (TOST) is invoked only for XT, LP andHS modes and only on Power-on Reset or wake-upfrom SLEEP.

When VDD rises very slowly, it is possible that theTPWRT time-out and TOST time-out will expire beforeVDD has reached its final value. In this case(Figure 6-9), an external Power-on Reset circuit maybe necessary (Figure 6-5).

FIGURE 6-5: EXTERNAL POWER-ONRESET CIRCUIT (FORSLOW VDD POWER-UP)

6.5 Power-up Timer (PWRT)

The Power-up Timer (PWRT) provides a fixed 72 msnominal time-out (TPWRT) from POR (Figures 6-6through 6-9). The Power-up Timer operates on aninternal RC oscillator. The chip is kept in RESET aslong as the PWRT is active. The PWRT delay allowsthe VDD to rise to an acceptable level (possible excep-

VDD

D

VDD

R

C

R1MCLR

PIC16FXX

tion shown in Figure 6-9).

A configuration bit, PWRTE, can enable/disable thePWRT. See Register 6-1 for the operation of thePWRTE bit for a particular device.

The power-up time delay TPWRT will vary from chip to

chip due to VDD, temperature, and process variation.See DC parameters for details.

Note 1: External Power-on Reset circuit is requiredonly if VDD power-up rate is too slow. Thediode D helps discharge the capacitorquickly when VDD powers down.

2: R < 40 k is recommended to make surethat voltage drop across R does not exceed

0.2V (max leakage current spec on MCLRpin is 5 A). A larger voltage drop willdegrade VIH level on the MCLR pin.

3: R1 = 100 to 1 k will limit any current flow-ing into MCLR from external capacitor C, inthe event of a MCLR pin breakdown due toESD or EOS.


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FIGURE 6-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 6-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUTTOST

OST TIME-OUT

INTERNAL RESET

FIGURE 6-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISETIME

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST

OST TIME-OUT

INTERNAL RESET


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TO PD Condition

1 1 Power-on Reset0 x Illegal, TO is set on PORx 0 Illegal, PD is set on POR0 1 WDT Reset (during normal operation)0 0 WDT Wake-up1 1 MCLR during normal operation1 0 MCLR during SLEEP or interrupt

wake-up from SLEEP

FIGURE 6-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD):SLOW VDD RISE TIME

V1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST

OST TIME-OUT

INTERNAL RESET

When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD

has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.

6.7 Time-out Sequence andPower-down Status Bits (TO/PD)

On power-up (Figures 6-6 through 6-9), the time-outsequence is as follows:

1. PWRT time-out is invoked after a POR hasexpired.

2. Then, the OST is activated.

The total time-out will vary based on oscillator configu-ration and PWRTE configuration bit status. For exam-ple, in RC mode with the PWRT disabled, there will beno time-out at all.

TABLE 6-5: TIME-OUT IN VARIOUSSITUATIONS

Since the time-outs occur from the POR pulse, if MCLRis kept low long enough, the time-outs will expire. Thenbringing MCLR high, execution will begin immediately(Figure 6-6). This is useful for testing purposes or tosynchronize more than one PIC16F84A device whenoperating in parallel.Table 6-6 shows the significance of the TO and PD bits.Table 6-3 lists the RESET conditions for some specialregisters, while Table 6-4 lists the RESET conditionsfor all the registers.

TABLE 6-6: STATUS BITS AND THEIRSIGNIFICANCE

OscillatorConfiguration

Power-up Wake-upfrom

SLEEPPWRT

EnabledPWRT

Disabled

XT, HS, LP72 ms +

1024TOSC 1024TOSC 1024TOSC

RC 72 ms


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6.9 Context Saving During Interrupts

During an interrupt, only the return PC value is savedon the stack. Typically, users wish to save key registervalues during an interrupt (e.g., W register andSTATUS register). This is implemented in software.

The code in Example 6-1 stores and restores the

STATUS and W registers values. The user definedregisters, W_TEMP and STATUS_TEMP are the tem-porary storage locations for the W and STATUSregisters values.

Example 6-1 does the following:

a) Stores the W register.

b) Stores the STATUS register in STATUS_TEMP.

c) Executes the Interrupt Service Routine code.

d) Restores the STATUS (and bank select bit)register.

e) Restores the W register.

EXAMPLE 6-1: SAVING STATUS AND W REGISTERS IN RAMPUSH MOVWF W_TEMP ; Copy W to TEMP register,

SWAPF STATUS, W ; Swap status to be saved into WMOVWF STATUS_TEMP ; Save status to STATUS_TEMP register

ISR : :: ; Interrupt Service Routine: ; should configure Bank as required: ;

POP SWAPF STATUS_TEMP,W ; Swap nibbles in STATUS_TEMP register; and place result into W

MOVWF STATUS ; Move W into STATUS register; (sets bank to original state)

SWAPF W_TEMP, F ; Swap nibbles in W_TEMP and place result in W_TEMPSWAPF W_TEMP, W ; Swap nibbles in W_TEMP and place result into W

6.10 Watchdog Timer (WDT)

The Watchdog Timer is a free running On-Chip RCOscillator which does not require any externalcomponents. This RC oscillator is separate from theRC oscillator of the OSC1/CLKIN pin. That means thatthe WDT will run even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins of the device has beenstopped, for example, by execution of a SLEEPinstruction. During normal operation, a WDT time-outgenerates a device RESET. If the device is in SLEEPmode, a WDT wake-up causes the device to wake-upand continue with normal operation. The WDT can bepermanently disabled by programming configuration bitWDTE as a '0' (Section 6.1).

6.10.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (withno prescaler). The time-out periods vary withtemperature, VDD and process variations from part topart (see DC specs). If longer time-out periods aredesired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT under software control bywriting to the OPTION_REG register. Thus, time-outperiods up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDTand the postscaler (if assigned to the WDT) and pre-vent it from timing out and generating a deviceRESET condition.The TO bit in the STATUS register will be cleared upona WDT time-out.


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6.10.2 WDT PROGRAMMINGCONSIDERATIONS

It should also be taken into account that under worstcase conditions (VDD = Min., Temperature = Max., Max.WDT Prescaler), it may take several seconds before aWDT time-out occurs.

FIGURE 6-11: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source(Figure 5-2)

WDT Timer

WDT

Enable Bit

0M

1 U

X

PSA

Postscaler

8

8 - to -1 MUX

PS2:PS0

To TMR0 (Figure 5-2)

0 1

MUX PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION_REG register.

TABLE 6-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPower-on

Reset

Value on allother

RESETS

2007h Config. bits (2) (2) (2) (2) PWRTE(1) WDTE FOSC1 FOSC0 (2)81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111Legend: x= unknown. Shaded cells are not used by the WDT.Note 1: See Register 6-1 for operation of the PWRTE bit.

2: See Register 6-1 and Section 6.12 for operation of the code and data protection bits.


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Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)

Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h)

T

6.11 Power-down Mode (SLEEP)

A device may be powered down (SLEEP) and laterpowered up (wake-up from SLEEP).

6.11.1 SLEEP

The Power-down mode is entered by executing the

SLEEP instruction.If enabled, the Watchdog Timer is cleared (but keepsrunning), the PD bit (STATUS) is cleared, the TO bit(STATUS) is set, and the oscillator driver is turnedoff. The I/O ports maintain the status they had beforethe SLEEP instruction was executed (driving high, low,or hi-impedance).

For the lowest current consumption in SLEEP mode,place all I/O pins at either VDD or VSS, with no externalcircuitry drawing current from the I/O pins, and disableexternal clocks. I/O pins that are hi-impedance inputsshould be pulled high or low externally to avoid switch-ing currents caused by floating inputs. The T0CKI inputshould also be at VDD or VSS. The contribution from

on-chip pull-ups on PORTB should be considered.The MCLR pin must be at a logic high level (VIHMC).

It should be noted that a RE SET generated by aWDTtime-out does not drive the MCLR pin low.

6.11.2 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one ofthe following events:1. External RESET input on MCLR pin.

2. WDT wake-up (if WDT was enabled).

3. Interrupt from RB0/INT pin, RB port change, or

data EEPROM write complete.Peripherals c

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