VHDL Simulation Tutorials [INFN Torino Wiki]

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VHDL simulation tutorials

A simple Shift Register

Project outlineFirst of all, we have to decide what kind of project we're going to do in VHDL language.

In the following tutorial we'll develop a very simple shift register in order to understand the firststeps of ASIC programming. It is necessary to create a well organized working space in order toavoid confusion among files and directories that we'll use during the digital flow.

To be ordered is extremely important in life! and also here could let you avoid wast ing a lot oftime

In the following picture you can see an example of directories' tree for our project:

In the

projectsdirectory another directory shiftregisterhas been created, and this one willcontain all the files pertinent with the project (with the exception of the technology libraries)

Even if we won't use immediately all the directories, we can create them right now; in the

shiftregisterdirectory we can see:

lec(logic equivalence check)

pnr_shiftregister(ci servir per ilplace and route)syn_shiftregister(ci serve per la sintesi, ed la cartella che prenderemo in

considerazione ora).

Into syn_shiftregisterdirectory we can prepare others directories:


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db

netlist_in

netlist_out

reports

scripts

sdc

work

Now, in the netlist_indirectory, we can create two empty files with a .vhdextension:

the first, we will name shiftregister.vhd(this is the source file), the second, tb_shiftregister.vhd(this is the test bench file).

Note that, in order to have a simpler life in the later steps (simulation and synthesis) and in order

to recognize immediately which file is a source fileand which is a test benchfile, wecould name the source file with the same name of the entity, (i.e. shiftregister.vhd) andthe test bench file with the same name of the source file with the exception of a tb_suffix (i.e.tb_shiftregister.vhd).

In the case we have some test benches, we can also enumerate them, in this way:tb01_shiftregister.vhd, tb02_shiftregister.vhd , tb350_shiftregister.vhd etc. Here we'll useonly one test bench, so we won't enumerate the file.

VHDL implementation

In our example, we decided to implement a shift register in which we have serial input and output(they're standard logic); so we have just defined an object like this:

Now we can decide if we want a positive or a negative logic; in the first case we consider theTRUE case equal to 1 and the FALSE case equal to 0; in the second one, it is just the opposite.

We can write, then, the VHDL model including the process that allow us to select the rightoutput:

-- *********************************************

-- Title : 3-bit Shift-Register

-- Author : Serena Panati

-- File : shiftregister.vhd

-- Version : 1.0

-- Generated : 09.03.2013

-- *********************************************

----------------------------------------

-- Libraries----------------------------------------

library ieee ;

use ieee.std_logic_1164.all;

----------------------------------------

-- Entity declaration


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----------------------------------------

entity shiftregister is

port( data_in: in std_logic;

sr_clock: in std_logic;

shift: in std_logic;

Q: out std_logic

);

end shiftregister;

----------------------------------------

-- Architecture

----------------------------------------architecture shiftregister_archi of shiftregister is

-- inizializzazione del segnale S

signal S: std_logic_vector(2 downto 0):="111";

begin

process(data_in, sr_clock, shift, S)

begin

if sr_clock'event and sr_clock='1' then

if shift = '1' then

S(0)


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signal T_data_in: std_logic;

signal T_sr_clock: std_logic;

signal T_shift: std_logic;

signal T_Q: std_logic;

begin

instance_shiftregister: shiftregister

port map (

data_in => T_data_in,

sr_clock => T_sr_clock,

shift => T_shift,Q => T_Q);

----------------------------------------

-- clk generating process

----------------------------------------

generate_clock : process

begin

T_sr_clock


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Line

assert FALSE report "End of simulation" severity FAILURE;

represents a trick in order to stop the simulation when the last values is forced, without stoppingit using the GUI of Cadence SimVision.

The last part of this code represents the configuration file that connects each component to itsentity.

----------------------------------------

-- Configuration File

----------------------------------------

configuration tbc_shiftregister_archi of tb_shiftregister isfor tb_shiftregister_archi

for all: shiftregister

use entity work.shiftregister(shiftregister_archi);

end for;

end for;

end tbc_shiftregister_archi ;

Simulation

For the simulation we can use Cadence NCLaunch e SimVision tools.

Let's move from homedirectory to netlist_in:

cd projects/shiftregister/syn_shiftregister/netlist_in/

and let's write

cdsterm

and let's press Enter; then we can choose the tool with:

1d

and press Enter another time; then let's select the technology we want to use; in this example,we'll choose Tower Jazz, so:

5a


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and then Enter. A new terminal will open, and in this window writing

nclaunch &

and pressing Enter, the window showed in the following picture will appear.

Now, it is possible to compile the file by clicking two times on shiftregister.vhd(left column) orby selecting the name and then clicking on the VHDL button (with a gear symbol).

Below into the console, it is possible to see the script of the command, error signals (if therewere), memory and CPU use; in our case:

nclaunch> ncvhdl -work worklib -cdslib /export/elt78xl/disk0/users/panati/

projects/shiftregister/syn_shiftregister/netlist_in/cds.lib -logfile

ncvhdl.log -errormax 15 -update -linedebug -status /export/elt78xl/

disk0/users/panati/projects/shiftregister/syn_shiftregister/

netlist_in/shiftregister.vhd

ncvhdl(64): 10.20-s073: (c) Copyright 1995-2011Cadence Design Systems, Inc.

ncvhdl_p: Memory Usage - 10.4M program + 13.2M data = 23.6M total

ncvhdl_cg: Memory Usage - 7.6M program + 10.7M data = 18.3M total

ncvhdl: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.3s, 8.7% cpu)

The procedure for the test bench is totally the same.

In the case of error, i.e. forgetting in line 49 the last semicolon:

T_sr_clock


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the line in which there it is (49).

In this way it is possibile debugging codes until they are without errors or problems.

Then we can elaborate our project. In the right column, under the worklibdirectory, there arethree IC symbols, with some titles:

shiftregister

tb_shiftregistertbc_shiftregister

we have to select the tbc_shiftregister(configuration file) and then clicking on the Elaboration

button (with a clip image, Launch Elaborator).


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If there aren't problems, in console we will see only control messages (CPU and memory use) likethis:

nclaunch> ncelab -work worklib -cdslib /export/elt78xl/disk0/users/

panati/projects/shiftregister/syn_shiftregister/netlist_in/cds.lib

-logfile ncelab.log -errormax 15 -access +wc -status

worklib.tbc_shiftregister_archi

ncelab(64): 10.20-s073: (c) Copyright 1995-2011 Cadence Design Systems, Inc.

ncelab: Memory Usage - 31.7M program + 30.9M data = 62.6M total

ncelab: CPU Usage - 0.0s system + 0.0s user = 0.1s total (0.7s, 10.0% cpu)

At the same time, in the Snapshot directory (second column under worklib) worklib:tbc_shiftregister_archi:configurationfile will appear: we have to select it andthen click on the Simulator button (Launch Simulator, to the right of Launch

Elaborator).


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In this moment two SimVision windows will open: DesignBrowserand Console:


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Let's consider the DesignBrowserwindow: expanding the menu in the left column

(WORKLIB:TB$\_$SHIFTREGISTER(TB_SHIFTREGISTER_ARCHI))we can see thetwo processes of the test bench (generate_clke values_gen) and the instanceinstance_shiftregister.

By clicking on (WORKLIB:TB_SHIFTREGISTER(TB_SHIFTREGISTER_ARCHI))

in the right column signals will appear.


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By clicking on the instance (instance_shiftregister) input and output will

appear.


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Now it is possible to select signals or pin in order to simulate them; in this example both groupsare simulated.

Starting by (WORKLIB:TB_SHIFTREGISTER(TB_SHIFTREGISTER_ARCHI))we canselect the signals in the right column (doing this they'll appear highlighted) and then we can clickon the button with a red/green square waveform; then a new window named Waveform 1willopen.

Now we have to select some (or all) the line in the left column and by clicking Menu Simulations Run (or simply F2) the waveforms will be drawn.

Files hdl.var e cds.lib


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The first time the simulation is done, two files are created automatically in the netlist_infolder:

cds.lib

hdl.var

containing some information about the libraries for the simulation.

If we are using a choosen technology, in order not to have problems with the post-synthesis

simulation, we can add in these files the paths of our technology libraries.

In this example, we are using Tower Jazz 180 nm technology (if you are using another technology,please ask your supervisor what path you need).

So, after the first simulation we have, i.e., in cds.lib:

define worklib /export/elt78xl/disk0/users/panati/projects/shiftregister/

syn_shiftregister/netlist_in/INCA_libs/worklib

include $CDS_INST_DIR/tools/inca/files/cds.lib

and in hdl.var:

define WORK worklib

include $CDS_INST_DIR/tools/inca/files/hdl.var

Then, we can change only the cds.libin this way:

define worklib /export/elt78xl/disk0/users/panati/projects/shiftregister

/syn_shiftregister/netlist_in/INCA_libs/worklib

include $CDS_INST_DIR/tools/inca/files/cds.lib

DEFINE tsl18fs120_lib /usr/tj_lib/TS18IS_SC/tsl18fs120/verilog/tsl18fs120_lib

SimVision Tip&Tricks

Print the waveforms

It is possible to export the waveforms in .pdf or .ps format (color or black and white), just openFile Print Window.

Here you can choose the document path, the t itle, the page size (A4, A5), orientation, colorsetc.


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Visual arrangement

By using top-right buttons (+, -, =, magnifying glass) it is possible to enlarge or shrink thewaveform view.

The =symbol allows a synoptic vision.

Changing test bench forced values

You can change forced values in the test bench without c losing Simvision. After the change, youcan click on Simulation Reinvoke simulator: in this way you can restart the Run (F2) with thenewer values.

Changing values/color of waveforms

From column Cursor(the second beginning to the right) by right clicking it is possible to changethe waveform color and the signal coding (binary, exaadecimal).

Default for the standard logic: binary.

Default for the standard logic vectors: exadecimal.


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Schematic Tracer

By selecting some or all signals and by clicking on the button Schematic Tracer(the buttonwith some little black wired boxes) it is possibile to have a useful tracer.

Last Update: Serena Panati [mailto:[email protected]]Nov 24st 2013

vls i/workbook/digital/hdls im/vhdl_tutorials.txt Ult ima modif ica: 24/11/2013 20:38 da panati
mailto:[email protected]

VHDL Simulation Tutorials [INFN Torino Wiki]

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