Spi Seminar

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    Serial Peripheral Interface (SPI)

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    Outline:

    Intoduction

    Features

    Block Diagram and Signal Description

    Internal structure

    Operating Modes

    SPI Registers

    Timing Diagram

    Advantages

    Disadvantages Conclusion

    References

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    Introduction

    Why Serial Communication?

    SPI was Invented by MOTOROLA, and supported in many silicon products.

    SPI is used to transfer data between microcontroller and peripheral, board to board.

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    Features

    Serial communicationFull Duplex

    Synchronous Communication

    Master Mode And Slave Mode

    High Data Rates

    Serial clock with Programmable Polarity and Phase

    Different Operating Modes

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    Block Diagram And Signal Description

    SPIMaster

    SCLK

    MOSIMISOSS1

    SS2SS3

    SCLKMOSIMISOSS1

    Slave 1

    SCLKMOSIMISOSS2

    Slave 2

    SCLKMOSIMISO

    SS3

    Slave 3

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    Internal Architecture

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    Operating Modes

    SPI functions in three different modes :

    1.Run Mode:

    This is the basic mode of operation.

    2.Wait Mode:

    SPI operation in wait mode is a configurable low power mode, controlled by theSPISWAI bit located in the SPICR2 register.

    3.Stop Mode :

    The SPI is inactive in stop mode for reduced power consumption.

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    SPI Registers

    SPI uses four different registers.

    1. SPI Control Register 1 (SPICR1)

    2. SPI Control Register 2 (SPICR2)

    3. SPI Baud Rate Register (SPIBR)

    4. SPI Status Register (SPISR)

    5. SPI Data Register (SPIDR)

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    SPI Control Register 1 (SPICR1)SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE

    SPIE:SPI Interrupt Enable

    SPE:SPI System Bit:

    SPTIE:SPI Transmit Interrupt Enable

    MSTR:SPI Master/Slave Mode Select Bit

    CPOL:SPI Clock Polarity Bit

    CPHA:SPI Clock Phase Bit

    SSOE: Slave Select Output Enable

    LSBSE: LSB First Enable

    1 = SPI interrupts enabled., 0 = SPI interrupts disabled.

    1=SPI Enabled, 0 = SPI Disabled

    1=Interrupt Enable,0=Interrupt Disable

    1=Master Mode, 0=Slave Mode

    1=Active Low Clock, 0=Active High Clock

    1=Sampling of data occurs at even edges,0=Sampling of data occurs at odd edges

    1=Data is Transferred with LSB first,0=Data is Transferred with MSB first

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    SPI Control Register 2 (SPICR2)

    Reserved

    MODFEN: Mode Fault Enable Bit

    MODFEN BIDROE SPISWAI SPC0

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    SPI Baud Rate Register (SPIBR)

    SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0

    SPPR2-SPPR0 : Baud rate Pre selection Bits

    Reserved

    SPR2 SPR0: Baud Rate Selection BitsBaudRateDivisor = (SPPR + 1) 2 (SPR + 1)

    Bus ClockBaudRateDivisorBaud Rate =

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    SPI Status Register (SPISR)

    SPIF SPTEF MODF

    Reserved

    SPIF:Interrupt Flag 1 = New Data Copied to SPIDR, 0=Transfer not Complete

    SPTEF: Transmit Empty Interrupt Flag 1=Data Register Empty, 0=Register not Empty

    MODF: Mode Fault Flag 1=Fault has occurred, 0=Fault has not occurred

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    SPI Data Register (SPIDR)

    Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

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    Timing DiagramCPHA = 0 Transfer Format

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    Conti CPHA = 1 Transfer Format

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    Advantages

    Extremely efficient for single master, single slave application as compared I2C.

    Higher Data Rates as compared I2C.

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    Disadvantages

    SPI master does not have any acknowledgement mechanism to confirm thereceipt of data

    Due to its lack of built in device addressing,SPI requires more efforts and more

    hardware resource.

    It does not support multi master configuration.