Processo CMOS 1

Progettazione di circuiti e sistemi VLSI

Anno Accademico 2011-2012

Lezione 2

9.3.2012

Processo di fabbricazione CMOS

Processo CMOS 2

CMOS Process

p-

P+

CMOS Process

Processo CMOS 3

A Modern CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

Dual-Well Trench-Isolated CMOS Process

Processo CMOS 4

Circuit Under Design

VDD VDD

Vin Vout

M1

M2

M3

M4

Vout2

Processo CMOS 5

oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic Process

Processo CMOS 6

Patterning of SiO2Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-lightPatternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

Processo CMOS 7

CMOS Process at a GlanceDefine active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

Processo CMOS 8

CMOS Process Walk-Through

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epi SiO2

3SiN

4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)

Processo CMOS 9

CMOS Process Walk-Through

SiO2(d) After trench filling, CMP planarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

n

(f) After p-well andVTn adjust implants

p

Processo CMOS 10

CMOS Process Walk-Through

(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+ source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2

Processo CMOS 11

CMOS Process Walk-Through

(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.

AlSiO2

Processo CMOS 12

Design Rules

Processo CMOS 13

3D Perspective

Polysilicon Aluminum

Processo CMOS 14

Design Rules

• Interface between designer and process engineer

• Guidelines for constructing process masks• Unit dimension: Minimum line width

– scalable design rules: lambda parameter corrispondente a metà della dimensione minima

– absolute dimensions (micron rules)

Processo CMOS 15

CMOS Process LayersLayer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green

Processo CMOS 16

Layers in 0.25 mm CMOS process

Processo CMOS 17

Intra-Layer Design Rules

Metal2 4

3

10

90

Well

Active3

3

Polysilicon2

2

Different PotentialSame Potential

Metal1 3

32

Contactor Via

Select2

or6

2Hole

Processo CMOS 18

Transistor Layout

1

2

5

3

Tran

sist

or

Processo CMOS 19

CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

Processo CMOS 20

Layout Editor

Processo CMOS 21

Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities• Only topology is important• Final layout generated by

“compaction” program

Processo CMOS 22

Packaging

Processo CMOS 23

Packaging Requirements

• Electrical: Low parasitics• Mechanical: Reliable and robust• Thermal: Efficient heat removal• Economical: Cheap

Processo CMOS 24

Bonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding

Processo CMOS 25

Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads

Processo CMOS 26

Flip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers

Processo CMOS 27

Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

Processo CMOS 28

Package Types

2

3

Ball grid array

Processo CMOS 29

Package Parameters