FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! •...

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FPGA and more Marco D. Santambrogio: [email protected] Politecnico di Milano EG7 – 21 Aprile 2016 Ver. 0 del 21 Aprile

Transcript of FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! •...

Page 1: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

FPGA and more!

Marco D. Santambrogio: [email protected]!Politecnico di Milano!

EG7 – 21 Aprile 2016!!

Ver. 0 del 21 Aprile!

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Logistica: introduzione!•  31 Marzo – 7 Aprile!

–  Impariamo a parlare del nostro progetto: presentazioni e pitch!

•  14 Aprile!–  Impariamo a scrivere del nostro progetto: LaTeX!

•  21 Aprile!–  Impariamo a realizzare il nostro progetto: FPGA, queste

sconosciute!!

•  28 Aprile!–  Impariamo a condividere il nostro progetto: git e repository

condivisi!

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Logistica: C/Python!

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•  Dal 5 Maggio al 30 Giugno!–  8 incontri da 2h cad: apprendimenti strumenti nuovi!

•  Luglio!–  3 (7/14/21) Incontri da 4h cad: per mettere tutto

insieme!–  23-24 Luglio: Xilinx Hackathon!

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Team C!•  Riccardo Cavadini, Marta Bracco!•  Stephen Bono!•  Manuela Legnardi, Federica Ioli !•  Tommaso Ciceri, Bianca Falcone!•  Matteo Arlotti, Carlo Casalini!•  Davide Berretta, Paola Bahiti!•  Nicolò Grassi, Matteo Greco!•  Marina Gnocco, Federica Loizzo!•  Elisa Forzinetti, Denise Fumagalli!•  Elena Balzan, Rossella Damiano!•  Angela Colella, Chiara Alberti!

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TUTTI GLI ALTRI

TEAM PYTHON

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Logistica: Maggio/Giugno!

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•  5 Maggio!•  12 Maggio!•  19 Maggio!•  26 Maggio!•  10 Giugno!•  16 Giugno!•  23 Giugno!•  30 Giugno!

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Logistica: Maggio/Giugno!

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•  5 Maggio!•  12 Maggio!•  19 Maggio!•  26 Maggio!•  10 Giugno!•  16 Giugno!•  23 Giugno!•  30 Giugno! PRENDERE LE MISURE

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Logistica: Maggio/Giugno!

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•  5 Maggio!•  12 Maggio!•  19 Maggio!•  26 Maggio!•  10 Giugno!•  16 Giugno!•  23 Giugno!•  30 Giugno!

27 /5/16

CONTINUE OR NOT?

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Logistica: Maggio/Giugno!

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•  5 Maggio!•  12 Maggio!•  19 Maggio!•  26 Maggio!•  10 Giugno!•  16 Giugno!•  23 Giugno!•  30 Giugno! CHALLENGE ACCEPTED

DEAL!

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Xilinx Hackathon!•  Hack!–  Evento per approfondire/sfidarsi su specifiche

tecnologie tramite!

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Xilinx Hackathon!•  Hackathon!–  Evento per approfondire/sfidarsi su specifiche

tecnologie tramite!–  più giorni (marathon) di coding su idee/problemi

interessanti!!

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Xilinx Hackathon!•  Hackathon!–  Evento per approfondire/sfidarsi su specifiche

tecnologie tramite!–  più giorni (marathon) di coding su idee/problemi

interessanti!

•  Oggi 23-24 Luglio… potremmo spostarto al:!–  15-16 Luglio?!–  16-17 Luglio?!–  17-18 Luglio?!

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Gantt Chart!•  Grafico a barre che rappresenta le attività per

blocchi nel tempo.!–  L'inizio e la fine del blocco corrispondono all'inizio

ed alla fine dell'attività.!

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Gantt Chart: esempio!

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Analisi SWOT!•  Aiutare ad identificare le Forze (Strengths),

Debolezze (Weaknesses), Opportunità (Opportunities) e Minacce (Threats)!–  I punti di forza e di debolezza sono fattori interni

che possono creare o distruggere valore. !–  Le opportunità e le minacce sono fattori esterni

incontrollabili che possono comportare la creazione o la distruzione del valore.!

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Analisi SWOT: esempio!

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SWOT AnalysisS • Work environment: NECST

• Availability of validated algorithms for identification process • Embedded system

W• Lack of knowledge and experience about FPGA • Challenging workflow • Team members new to projects • Device of non trivial size

O

• Other researchers interested in our project • Spreading of biometric technology • Importance of protection of biometric data T

• Little time wrt workload and school duties • Strong competitors • First approach to the market

• Project• Product

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Reconfigurable Computing!

DReAMS

FPGA based systems!exascale computing infrastructure!

CAD tools!Physical design!

High-level analysis and PLs!

http://hplusmagazine.com/2009/04/07/brain-chip/!

Page 18: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Reconfigurable Hardware

“Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher

performance than software, while maintaining a higher level of flexibility than hardware”

(K. Compton and S. Hauck, Reconfigurable Computing: a Survey of Systems and Software, 2002)

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Page 19: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

trend toward !higher levels !of integration!

Evolution of implementation technologies!

•  Logic gates (1950s-60s)!•  Regular structures for two-level logic

(1960s-70s)!–  muxes and decoders, PLAs!

•  Programmable sum-of-products arrays (1970s-80s)!–  PLDs, complex PLDs!

•  Programmable gate arrays (1980s-90s)!–  densities high enough to permit entirely new!

class of application, e.g., prototyping, emulation,!acceleration!

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Page 20: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Gate Array Technology (IBM - 1970s)!•  Simple logic gates!

–  combine transistors to!implement combinational!and sequential logic!

•  Interconnect!–  wires to connect inputs and!

outputs to logic blocks!•  I/O blocks!

–  special blocks at periphery!for external connections!

•  Add wires to make connections!–  done when chip is fabbed!

•  “mask-programmable”!–  construct any circuit!

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Page 21: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Field-Programmable Gate Arrays!•  Logic blocks!

–  to implement combinational!and sequential logic!

•  Interconnect!–  wires to connect inputs and!

outputs to logic blocks!•  I/O blocks!

–  special logic blocks at periphery!of device for external connections!!

•  Key questions:!–  how to make logic blocks programmable?!–  how to connect the wires?!–  after the chip has been fabbed !

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Page 22: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Commercial FPGA Companies

Lattice official webiste

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Page 23: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

IOB IOB IOB IOB

CLB CLB

CLB CLBIOB

IOB

IOB

IOB

Wiring Channels

Xilinx Programmable Gate Arrays!•  CLB - Configurable Logic

Block!•  Built-in fast carry logic!•  Can be used as memory!•  Three types of routing!

–  direct!–  general-purpose!–  long lines of various lengths!

•  RAM-programmable!–  can be reconfigured!

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Page 24: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Configurable Logic Blocks!•  CLBs made of Slices!–  sVirtex-E 2-slice!–  VIIP 4-slice!

•  Slices made of LookUp Tables (LUTs)!

•  LookUp Tables!–  4-input, 1 output functions!– Newest FPGA 2 6-input 2 output!

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Page 25: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Simplified CLB Structure!

Look-Up Table (LUT)

Q

QSET

CLR

DMUX

CLB

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Page 26: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Lookup Tables: LUTs!•  LUT contains Memory Cells to implement small logic functions!•  Each cell holds ‘0’ or ‘1’ .!•  Programmed with outputs of Truth Table!•  Inputs select content of one of the cells as output!!

!

16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM4-input

LUT

clock enable

set/reset

3 Inputs LUT -> 8 Memory Cells

SRAM

Static Random Access MemorySRAM cellsSRAM

3 – 6 Inputs

Multiplexer MUX

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Page 27: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Example: 4-input AND gate!

AB

C

D

O

A B C D O

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 0

1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1

Q

QSET

CLR

DMUXA

B

C

D

0000000000000001

Configuration bits

O

0

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Page 28: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

The Virtex CLB!

2-SliceVirtex-ECLB

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Page 29: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Details of One Virtex Slice!

Virtex-ESlice

Page 30: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Implements any Two 4-input Functions!

4-inputfunc>on

3-inputfunc>on;

registered

Virtex-ESlice

Page 31: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

CLB!SwitchBox

SLICE

TBUF

Y

X6766

75

74

SLICE_X66Y74

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4-SliceVIIPCLB

Page 32: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Interconnection Network!

CLB SB

SB SB

CLB

SB

CLB SB CLBConfigurable Logic Blocks

Interconnection Network

I/O Signals (Pins)

Configuration bits 1

0

0

00

0

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Page 33: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Example !

CLB0 SB0

SB1 SB2

CLB1

SB3

CLB2 SB4 CLB3

Input1

Input2

OutputInput3

•  Determine the configuration bits for the following circuit implementation in a 2x2 FPGA, with I/O constraints as shown in the following figure. Assume 2-input LUTs in each CLB.!

Q

QSET

CLR

DInput1Input2

Input3

Output

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CLBs configuration!

Q

QSET

CLR

DInput1Input2

Input3

Output

CLB 1 CLB 2

Q

QSET

CLR

DMUX

Input1Input2

0

0

0

1

Configuration bits

O

1 Q

QSET

CLR

DMUX

OInput3

0

1

1

0

Configuration bits

Output

0

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Page 35: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Placement: Select CLBs!

CLB0 SB0

SB1 SB2

CLB1

SB3

CLB2 SB4 CLB3

Input1

Input2

OutputInput3

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Page 36: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Routing: Select path!

CLB0 SB0

SB1 SB2

CLB1

SB3

CLB2 SB4 CLB3

Input1

Input2

OutputInput3

Configuration bits

SB1

1

0

0

00

0

Configuration bits

SB4

0

0

0

01

0

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Page 37: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Configuration Bitstream!•  The configuration bitstream must include ALL CLBs and

SBs, even unused ones!•  CLB0: 00011!•  CLB1: ?????!•  CLB2: 01100!•  CLB3: XXXXX!•  SB0: 000000!•  SB1: 000010!•  SB2: 000000!•  SB3: 000000!•  SB4: 000001!

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The configuration bitstream!

•  Occupation must be determined only on the basis of !–  Number of configuration words!–  Initial Frame Address Register (FAR) value!

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Frame and Configuration Memory!•  Virtex-II Pro !

–  Configuration memory is arranged in vertical frames that are one bit wide and stretch from the top edge of the device to the bottom!

–  Frames are the smallest addressable segments of the VIIP configuration memory space!•  all operations must act on whole configuration frames.!

•  Virtex-4 !–  Configuration memory is arranged in frames that are

tiled about the device!–  Frames are the smallest addressable segments of the

V4 configuration memory space!•  all operations must therefore act upon whole configuration

frames!

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Page 40: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Xilinx Virtex-4: frame organization !

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Some Definitions!•  Object Code: the executable active physical (either HW or

SW) implementation of a given functionality!!•  Core: a specific representation of a functionality. It is

possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)!

•  IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface)!

•  Reconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture!

!•  Reconfigurable Region: a portion of the device area used to

implement a reconfigurable core!

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Page 42: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Xilinx FPGA and Configuration Memory!

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FPGA EDA Tools!•  Must provide a design environment based on

digital design concepts and components (gates, flip-flops, MUXs, etc.)!

•  Must hide the complexities of placement, routing and bitstream generation from the user. Manual placement, routing and bitstream generation is infeasible for practical FPGA array sizes and circuit complexities.!

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Page 44: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

Computer-aided Design!•  Can't design FPGAs by hand!

–  way too much logic to manage, hard to make changes!!

•  Hardware description languages!–  specify functionality of logic at a high level!

•  Validation - high-level simulation to catch specification errors!–  verify pin-outs and connections to other system components!–  low-level to verify mapping and check performance!

•  Logic synthesis!–  process of compiling HDL program into logic gates and flip-flops!

•  Technology mapping!–  map the logic onto elements available in the implementation

technology (LUTs for Xilinx FPGAs)!

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Page 45: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

CAD Tool Path (cont’d)!•  Placement and routing!

–  assign logic blocks to functions!–  make wiring connections!

•  Timing analysis - verify paths!–  determine delays as routed!–  look at critical paths and ways to improve!

•  Partitioning and constraining!–  if design does not fit or is unroutable as placed split into multiple chips!–  if design it too slow prioritize critical paths, fix placement of cells, etc.!–  few tools to help with these tasks exist today!

•  Generate programming files - bits to be loaded into chip for configuration!

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Page 46: FPGA and more - Intranet DEIBhome.deib.polimi.it/.../FPGA/FPGAandMore_V1.pdf · FPGA EDA Tools! • Must provide a design environment based on digital design concepts and components

QUESTIONS?!

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Marco D. [email protected]!

http://www.necst.it