filter_pkg.vhd Fri Nov 28 22:54:25 2014

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1 library IEEE;2 use IEEE.STD_LOGIC_1164.all;3 use IEEE.numeric_std.all;4 5 package filter_pkg is6 7 --Cantidad de bits que tienen los coeficientes.8 constant coef_cantBits : natural := 23;9 --Cantidad de bits de las muestras del microfono

10 constant sample_cantBits : natural := 8;11 --Cantidad de coeficientes del filtro12 constant cantCoef : natural := 16;13 14 --Matriz que contiene varias muestras de 8 bits15 type sample is array(integer range ) of std_logic_vector(sample_cantBits - 1

downto 0);16 --Matriz que contiene varios coeficientes de 23 bits cada uno17 type coeficient is array(integer range ) of signed(coef_cantBits - 1 downto 0);18 19 end filter_pkg;20

clockDivider.vhd Fri Nov 28 22:29:16 2014

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1 library IEEE;2 use IEEE.STD_LOGIC_1164.ALL;3 use IEEE.NUMERIC_STD.ALL;4 5 entity clockDivider is6 ------------------------------ Puertos - clockDivider -------------------------------7 port(8 --INPUTS9 clk, reset: in std_logic;

10 11 --OUTPUTS12 tick20Khz: out std_logic13 );14 end clockDivider;15 16 ---------------------------- ARQUITECTURA - clockDivider -----------------------------17 architecture Behavioral of clockDivider is18 19 --Creo las senales correspondientes a la maquina de estados20 --Necesito al menos 13 bits para contar hasta 5000 (y llegar a frecuencia 20Khz)21 signal cont_reg, cont_next: unsigned(12 downto 0);22 23 24 begin25 -------------------------- Logica de estado actual -------------------------------26 process(clk, reset) begin27 28 if(reset='1') then29 cont_reg '0');30 elsif (rising_edge(clk)) then31 cont_reg

generadorDeFlanco.vhd Fri Nov 28 22:48:01 2014

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1 library IEEE;2 use IEEE.STD_LOGIC_1164.ALL;3 4 entity generadorDeFlanco is5 --------------------------- Puertos - generadorDeFlanco ------------------------------6 port(7 --INPUTS8 clk, reset : in std_logic;9 start : in std_logic;

10 11 --OUTPUTS12 done : out std_logic13 );14 end generadorDeFlanco;15 16 ------------------------- ARQUITECTURA - generadorDeFlancos --------------------------17 architecture Behavioral of generadorDeFlanco is18 19 type estados is (bajo, flanco, alto);20 signal state_reg, state_next : estados;21 22 begin23 24 -------------------------- Logica de estado actual -------------------------------25 process(clk,reset)26 begin27 if(reset = '1') then28 state_reg

generadorDeFlanco.vhd Fri Nov 28 22:48:01 2014

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58 if start = '0' then59 state_next

serieParalelo.vhd Sat Nov 29 13:45:11 2014

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1 library IEEE;2 use IEEE.STD_LOGIC_1164.ALL;3 use IEEE.NUMERIC_STD.ALL;4 use work.filter_pkg.all;5 6 entity serieParalelo is7 8 ------------------------------ Generics - serieParalelo ------------------------------9

10 generic (cantSalidas: natural := cantCoef); --Cantidad de salidas en paralelo11 12 ------------------------------ Puertos - serieParalelo -------------------------------13 port(14 15 --INPUTS16 clk, reset: in std_logic;17 start: in std_logic;18 input: in std_logic_vector(11 downto 0); -- 12 bits que vienen del Mic.19 20 --OUTPUTS21 --Cant. de salidas en paralelo22 output: out sample(cantSalidas-1 downto 0):= (others=>(others=>'0'));23 done: out std_logic24 );25 end serieParalelo;26 27 28 ------------------------- ARQUITECTURA - generadorDeFlancos --------------------------29 architecture Behavioral of serieParalelo is30 31 signal paralelo_reg, paralelo_next: sample(cantSalidas-1 downto 0):= (others=>(

others=>'0'));32 33 begin34 35 -------------------------- Logica de estado actual ---------------------------------36 process(clk, reset) begin37 if(reset='1') then38 paralelo_reg (others=>'0')); --Pongo la entrada en cero.39 elsif (rising_edge(clk)) then40 paralelo_reg

voiceFilter.vhd Sat Nov 29 03:22:24 2014

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1 library IEEE;2 use IEEE.STD_LOGIC_1164.ALL;3 use ieee.numeric_std.all;4 use work.filter_pkg.all;5 6 entity voiceFilter is7 ------------------------------ Puertos - voiceFilter -------------------------------8 port(9

10 --INPUTS11 clk,reset : in std_logic;12 filterStart : in std_logic;13 input : in sample(cantCoef-1 downto 0);14 15 --OUTPUTS16 filterDone : out std_logic;17 filteredSignal : out std_logic_vector(sample_cantBits-1 downto 0)18 19 );20 end voiceFilter;21 22 ---------------------------- ARQUITECTURA - voiceFilter ----------------------------23 architecture Behavioral of voiceFilter is24 25 --Este vector completa los 8 bits del mensaje con ceros para llevarlo a 23 y 26 --operar con los coeficientes27 constant ceros : std_logic_vector(coef_cantBits - sample_cantBits - 2 downto 0) :=

(others => '0');28 29 --Para guardar una muestra de la senal en 23 bits (para operar con los 30 --coeficientes)31 signal input_to_filter : signed(coef_cantBits-1 downto 0);32 --Como se multiplexan los productos entre la senal y los coeficientes del filtro,33 --esta senal es para manejar un coeficiente del filtro a la vez, en las operaciones.34 signal filter_Coef : signed(coef_cantBits-1 downto 0);35 --producto entre la senal retrasada i veces y el coeficiente i-esimo36 signal producto : signed(coef_cantBits + coef_cantBits - 1 downto 0);37 --sumas de los productos senal-coeficientes. (23 + 23) bits38 signal suma_reg, suma_next : signed(coef_cantBits + coef_cantBits downto 0);39 --Indices para los coeficientes (debido al multiplexado en el producto)40 signal coef_reg, coef_next : unsigned(3 downto 0);41 --Banderas de control42 signal procesando, procesamiento_Completado : std_logic;43 44 --Banderas para marcar el estado del filtro45 type filter_State is (esperandoDatos,ocupado,terminado);46 signal state_reg, state_next : filter_State;47 48 -- Coeficientes del filtro49 --vector de 16 coeficientes x 23 bits.50 signal coef_vector : coeficient(cantCoef-1 downto 0) :=51 (52 to_signed(1, coef_cantBits),53 to_signed(-1, coef_cantBits),54 to_signed(-64, coef_cantBits),55 to_signed(100, coef_cantBits),56 to_signed(-584, coef_cantBits),

voiceFilter.vhd Sat Nov 29 03:22:25 2014

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57 to_signed(969, coef_cantBits),58 to_signed(-3103, coef_cantBits),59 to_signed(9874, coef_cantBits),60 to_signed(9874, coef_cantBits),61 to_signed(-3103, coef_cantBits),62 to_signed(969, coef_cantBits),63 to_signed(-584, coef_cantBits),64 to_signed(100, coef_cantBits),65 to_signed(-64, coef_cantBits),66 to_signed(-1, coef_cantBits),67 to_signed(1, coef_cantBits)68 69 );70 71 begin72 73 74 ----------------------------------- CONTROL PATH ----------------------------------75 76 -------------------------- Logica de estado actual ------------------------------77 process(clk,reset)78 begin79 if(reset = '1') then80 state_reg

voiceFilter.vhd Sat Nov 29 03:22:25 2014

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114 115 --Uso esta variable auxiliar para llevar la entrada de 8 bits a 23, completando116 --con ceros, y agregando un bit de signo por delante.117 variable input_23bits : std_logic_vector(coef_cantBits-1 downto 0);118 119 begin120 case state_reg is121 122 ----------------------------- esperandoDatos ----------------------------123 when esperandoDatos =>124 125 procesando

voiceFilter.vhd Sat Nov 29 03:22:25 2014

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171 if(reset = '1') then172 coef_reg '0');173 elsif(rising_edge(clk)) then174 coef_reg

VoiceFilter_Top.vhd Sat Nov 29 01:43:03 2014

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1 library IEEE;2 use IEEE.STD_LOGIC_1164.ALL;3 use IEEE.NUMERIC_STD.ALL;4 use work.filter_pkg.all;5 6 7 entity VoiceFilter_Top is8 9 ----------------------------------- PUERTOS - TOP ----------------------------------

10 port(11 clk, reset: in std_logic;12 13 --Puertos de comunicacion Uart14 tx_out: out std_logic;15 tx_fifo_full: out std_logic;16 tx_data_ready: out std_logic;17 18 --Puertos de comunicacion con el modulo del microfono19 micData: in std_logic;20 micSCLK: out std_logic;21 micnCS: out std_logic22 23 );24 end VoiceFilter_Top;25 26 -------------------------------- ARQUITECTURA - TOP -------------------------------27 architecture Behavioral of VoiceFilter_Top is28 29 --------------------------------- Signals -----------------------------------30 --Senales que sirven como buffer para interconectar las salidas31 --de los distintos modulos, con la salida del modulo Top.32 33 --Mic IN34 signal tick20Khz: std_logic;35 36 --Mic OUT / generadorDeFlancos IN37 signal micDone: std_logic;38 39 --Mic, generadorDeFlancos OUT / serieParalelo IN40 signal micSample: std_logic_vector(11 downto 0);41 signal filterStart: std_logic;42 43 --serieParalelo OUT / voiceFilter IN44 signal parallel_data: sample(cantCoef-1 downto 0);45 signal serieParaleloStart: std_logic;46 47 --voiceFilter OUT / Uart IN48 signal tx_Start: std_logic;49 signal filteredSignal: std_logic_vector(sample_cantBits-1 downto 0);50 51 52 ------------------------------ COMPONENTES -----------------------------------53 ------------------------------ clockDivider ----------------------------------54 component clockDivider55 port(56 --INPUTS57 clk, reset: in std_logic;58 --OUTPUTS

VoiceFilter_Top.vhd Sat Nov 29 01:43:03 2014

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59 tick20Khz: out std_logic60 );61 end component;62 63 -------------------------------- micSampler ----------------------------------64 component PmodMICRefComp65 port(66 --General usage67 CLK : in std_logic;68 RST : in std_logic;69 --Pmod interface signals70 SDATA : in std_logic;71 SCLK : out std_logic;72 nCS : out std_logic;73 --User interface signals74 DATA : out std_logic_vector(11 downto 0);75 START : in std_logic;76 DONE : out std_logic77 );78 end component;79 80 -------------------------------- uart_tx_unit --------------------------------81 component uart_tx_unit82 generic(83 DBIT: integer := 8; -- # data bits84 SB_TICK: integer := 16; -- # ticks for stop bits, 16/24/3285 -- for 1/1.5/2 stop bits86 -- Selected: 1 stop bit87 DVSR: integer := 7; -- baud rate divisor88 -- DVSR = 100M/(16*baud rate)89 DVSR_BIT: integer := 3; -- # bits of DVSR90 FIFO_W: integer := 2 -- # addr bits of FIFO91 -- # words in FIFO=2^FIFO_W92 );93 port(94 clk, reset: in std_logic;95 96 -- interfaz hacia el usuario97 wr_uart: in std_logic;98 w_data: in std_logic_vector(7 downto 0);99 tx_full: out std_logic; --Flag de aviso.

100 101 -- interfaz hacia la PC102 tx: out std_logic; --Datos de salida a la PC103 data_ready : out std_logic104 );105 end component;106 107 -------------------------------- generadorDeFlanco ---------------------------108 component generadorDeFlanco109 port(110 --INPUTS111 clk, reset : in std_logic;112 start : in std_logic;113 --OUTPUTS114 done : out std_logic115 );116 end component;

VoiceFilter_Top.vhd Sat Nov 29 01:43:03 2014

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117 118 -------------------------------- serieParalelo -------------------------------119 component serieParalelo is120 generic (cantSalidas: natural := cantCoef); --Cantidad de salidas en paralelo121 port(122 --INPUTS123 clk, reset: in std_logic;124 start: in std_logic;125 input: in std_logic_vector(11 downto 0); -- 12 bits que vienen del Mic.126 --OUTPUTS127 --Cant. de salidas en paralelo128 output: out sample(cantSalidas-1 downto 0):= (others=>(others=>'0'));129 done: out std_logic130 );131 end component;132 133 -------------------------------- voiceFilter ---------------------------------134 component voiceFilter is135 port(136 --INPUTS137 clk,reset : in std_logic;138 filterStart : in std_logic;139 input : in sample(cantCoef-1 downto 0);140 --OUTPUTS141 filterDone : out std_logic;142 filteredSignal : out std_logic_vector(sample_cantBits-1 downto 0)143 );144 end component;145 146 begin147 --------------------------- INSTANCIAS A MODULOS --------------------------148 --Colocacion de modulos dentro del Top y mapeo de puertos.149 150 --Unidad que divide el clock de la FPGA para llevarlo a 10Khz151 clockDivider_unit: clockDivider --Para el saveToFile152 port map(clk => clk, reset => reset, tick20Khz => tick20Khz);153 154 --Unidadad del muestreador del microfono155 micSampler_unit: PmodMICRefComp156 port map(CLK => clk, RST => reset,157 SDATA => micData, SCLK => micSCLK, nCS => micnCS,158 DATA => micSample, START => tick20Khz, DONE => micDone);159 160 --Generador de flanco161 generadorDeFlanco_unit : generadorDeFlanco162 port map(clk => clk, reset => reset,163 start => micDone, done => serieParaleloStart);164 165 --Unidad conversora de serie a paralelo para pasar del microfono al filtro.166 serieParalelo_unit: serieParalelo --Para el conversor serie a paralelo167 generic map(cantSalidas => cantCoef)168 port map(clk => clk, reset => reset,169 input => micSample, output => parallel_data,170 start => serieParaleloStart, done => filterStart);171 172 --Unidadad del filtro173 voiceFilter_unit: voiceFilter --Para el filtro174 port map(clk => clk, reset => reset,

VoiceFilter_Top.vhd Sat Nov 29 01:43:04 2014

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175 filterStart => filterStart, filterDone => tx_Start,176 input => parallel_data, filteredSignal => filteredSignal);177 178 179 --Unidadad que guarda la salida del filtro en un archivo180 uart_unit: uart_tx_unit --Para el uart_tx_unit181 --Para elegir baudrate = 460800 baud182 generic map(DVSR => 14, DVSR_BIT => 4)183 port map(clk => clk, reset => reset,184 wr_uart => tx_Start, data_ready => tx_data_ready,185 w_data => filteredSignal, tx => tx_out,186 tx_full => tx_fifo_full);187 188 end Behavioral;