Progettazione di circuiti e sistemi VLSI

Sistemi Elettronici Programmabili

Progettazione di circuiti e sistemi VLSIProgettazione di circuiti e sistemi VLSI

Anno Accademico 2010-2011

Lezione 115.5.11

Memorie

(vedi anche i file pcs1_memorie.pdf pcs2_memorie.pdf – pcs3_memorie.pdf )

Chapter Overview

Memory Classification

Memory Architectures

The Memory Core

Periphery

Reliability Case Studies

Semiconductor Memory Classification

Read-Write MemoryNon-VolatileRead-Write

Memory

Read-Only Memory

E2PROM

RandomAccess

Non-RandomAccess

Mask-Programmed

Programmable (PROM)

Shift Register

Memory Timing: Definitions

Write cycleRead access Read access

Read cycle

Write access

Data written

Data valid

Memory Architecture: Decoders

Word 0

Word 1

Word 2

WordN- 2

WordN-1

Storagecell

M bits M bits

N words

K= log2N

Word 0

Word 1

Word 2

WordN- 2

WordN 1

Storagecell

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals

Decoder

Bit line2L2K

Word line

Sense amplifiers / Drivers

Column decoder

Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword

Contents-Addressable Memory

Address Decoder

I/O Buffers

Commands

29 Validity BitsPriority Encoder

Address Decoder

I/O Buffers

Commands

29 Validity Bits

Priority EncoderAddress Decoder

Data (64 bits)

I/O Buffers

Comparand

CAM Array29 words3 64 bits

Control LogicR/W Address (9 bits)

Commands

29 Validity Bits

Priority Encoder

Memory Timing: Approaches

DRAM TimingMultiplexed Adressing

SRAM TimingSelf-timed

Addressbus

RAS-CAS timing

Row Address

AddressBus

Address transitioninitiates memory operation

Address

Column Address

Read-Only Memory Cells

Diode ROM MOS ROM 1 MOS ROM 2

MOS OR ROM

Pull-down loads

BL[2] BL[3]

MOS NOR ROM

BL [0]

WL [1]

WL [2]

WL [3]

BL [1]

Pull-up devices

BL [2] BL [3]

MOS NOR ROM Layout

Programmming using theActive Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5 x 7)

MOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

Pull-up devices

BL[3]BL [2]BL [1]BL [0]

MOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8 x 7)

Programmming usingthe Metal-1 Layer Only

Equivalent Transient Model for MOS NOR ROM

• Word line parasitics– Wire capacitance and gate capacitance– Wire resistance (polysilicon)

• Bit line parasitics– Resistance not dominant (metal)– Drain and Gate-Drain capacitance

Model for NOR ROM VDD

Equivalent Transient Model for MOS NAND ROM

• Word line parasitics– Similar to NOR ROM

• Bit line parasitics– Resistance of cascaded transistors dominates– Drain/Source and complete gate capacitance

Model for NAND ROMVDD

Non-Volatile MemoriesThe Floating-gate transistor (FAMOS)

Floating gate

Source

Substrate

n+ n+_p

Device cross-section Schematic symbol

Floating-Gate Transistor Programming

- 5 V 0 V

Removing programming voltage leaves charge trapped

-2.5 V 5 V

Programming results in higher VT.

10 V 5 V 20 V

Avalanche injection

A “Programmable-Threshold” Transistor

“0”-state “1”-state

VWL VGS

“ON”

“OFF”

FLOTOX EEPROM

Floating gate

Source

Substratep

FLOTOX transistorFowler-Nordheim I-V characteristic

20–30 nm

EEPROM Cell

Absolute threshold controlis hardUnprogrammed transistor might be depletion 2 transistor cell

Flash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1source n1drainprogramming

Many other options …

Basic Operations in a NOR Flash Memory:Erase

cell arrayBL0 BL1

open open

Basic Operations in a NOR Flash Memory:Write

BL0 BL1

6 V 0 V

Basic Operations in a NOR Flash Memory:Write

BL0 BL1

6 V 0 V

Basic Operations in a NOR Flash Memory:Read

BL0 BL1

1 V 0 V

NAND Flash Memory

Unit Cell

Word line(poly)

Source line(Diff. Layer)

Courtesy Toshiba

FGGateOxide

NAND Flash Memory

Word linesSelect transistor

Bit line contact Source line contact

Active area

Courtesy Toshiba

Characteristics of State-of-the-art NVM

Read-Write Memories (RAM) STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended

6-transistor CMOS SRAM Cell

CMOS SRAM Analysis (Read)WL

M1VDDVDD VDD

Q = 1Q = 0

Cbit Cbit

CMOS SRAM Analysis (Read)

Voltage rise [V]

1 1.2 1.5 2Cell Ratio (CR)

CMOS SRAM Analysis (Write)

BL = 1 BL = 0

CMOS SRAM Analysis (Write)

Resistance-load SRAM Cell

Static power dissipation -- Want RL largeBit lines precharged to VDD to address tp problem

SRAM Characteristics

3-Transistor DRAM Cell

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn

VDD2VT

DVVDD2VTBL2

1-Transistor DRAM Cell

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

VDD2VT

sensing

Write 1 Read 1

VDD /2 V

V BL VPRE– VBIT VPRE–CS

CS CBL+------------= =V

DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

1-T DRAM Cell

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

M1 wordline

Diffusedbit line

Polysilicongate

Polysiliconplate

Capacitor

Cross-section Layout

Metal word line

Field Oxiden+ n+

Inversion layerinduced byplate bias

Static CAM Memory Cell

••• •••

••• CAM

Bit Bit

Wired-NOR Match Line

Match M1

M4 M5M8 M9

••• CAM

Bit Bit

CAM in Cache Memory

Address Decoder

Hit Logic

Input Drivers

Tag HitAddress

Sense Amps / Input Drivers

DataR/W

Periphery

Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry

Row Decoders

Collection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder

Hierarchical Decoders

• • •

A2A3A2A 3A2A3

A3 A3A 0A0

A0A 1A 0A1A0A1A0A1

A 1 A1

Multi-stage implementation improves performance

NAND decoder usingNAND decoder using2-input pre-decoders2-input pre-decoders

Dynamic Decoders

Precharge devices

A0A0 A1A1

2-input NOR decoder 2-input NAND decoder

Sense Amplifiers

Iav----------------=

make V as smallas possible

smalllarge

Idea: Use Sense Amplifer

outputinput

s.a.smalltransition

Differential Sense Amplifier

Directly applicable toSRAMs

bitbit

Differential Sensing ― SRAMVDD

Diff.SenseAmp

(a) SRAM sensing scheme (b) two stage differential amplifier

SRAM cell i

Output

x2x 2x

Latch-Based Sense Amplifier (DRAM)

Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.

Other Circuits for Memory Periphery

• Charge-based Amplifiers• Single-to Differential Conversion• Voltage Regulators• Charge pumps

and other solutions…

Reliability and Yield

Noise Sources in 1T DRam

Ccross

electrode

a-particles

leakage CS

BL substrate Adjacent BL

Alpha-particles (or Neutrons)

1 Particle ~ 1 Million Carriers

a-particle

Yield curves at different stages of process maturity(from [Veendrick92])

Redundancy

MemoryArray

Column Decoder

Row Decoder

Redundantrows

Redundantcolumns

RowAddress

ColumnAddress

FuseBank:

Error-Correcting Codes

Example: Hamming Codes

e.g. B3 Wrong

Redundancy and Error Correction

Trends in Memory Cell Area

From [Itoh01]

Progettazione di circuiti e sistemi VLSI

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